MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 336

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Multi-Master IIC Interface (MMIIC)
16.6.7 MMIIC CRC Data Register (MMCRCDR)
Data Sheet
336
Address:
In slave mode, the data in MMDRR is:
In master mode, the data in the MMDRR is:
When the MMDRR is read by the CPU, the receive buffer full flag is
cleared (MMRXBF = 0), and the next received data is loaded to the
MMDRR. Each time when new data is loaded to the MMDRR, the
MMRXIF interrupt flag is set, indicating that new data is available in
MMDRR.
The sequence of events for slave receive and master receive are
illustrated in
When the MMIIC module is enabled, MMEN = 1, and the CRC buffer full
flag is set (MMCRCBF = 1), data in this read-only register contains the
generated CRC byte for the last byte of received or transmitted data.
A CRC byte is generated for each received and transmitted data byte
and loaded to the CRC data register. The MMCRCBF bit will be set to
indicate the CRC byte is ready in the CRC data register.
Reading the CRC data register clears the MMCRCBF bit. If the CRC
data register is not read, the MMCRCBF bit will be cleared by hardware
before the next CRC byte is loaded.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
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the calling address from the master when the address match flag
is set (MMATCH = 1); or
the last data received when MMATCH = 0.
the last data received.
Figure 16-10. MMIIC CRC Data Register (MMCRCDR)
MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0
$004E
Bit 7
0
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Figure
= Unimplemented
6
0
16-12.
5
0
4
0
MC68HC908AP Family — Rev. 2.5
3
0
2
0
1
0
MOTOROLA
Bit 0
0