HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 178

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6. Bus Controller
6.5
6.5.1
When the H8/3008 chip accesses external space, it can insert a 1-state idle cycle (T
cycles in the following cases: when read accesses between different areas occur consecutively, and
when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible,
for example, to avoid data collisions between ROM, which has a long output floating time, and
high-speed memory, I/O interfaces, and so on.
The initial value of the ICIS1 and ICIS0 bits in BCR is 1, so that idle cycle insertion is performed
in the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is
inserted, and a data collision is prevented.
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.19 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Rev.4.00 Aug. 20, 2007 Page 134 of 638
REJ09B0395-0400
Address bus
Idle Cycle
Operation
Data bus
RD
φ
Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
T
1
Long buffer-off time
T
2
T
3
T
1
T
2
Data collision
Address bus
Data bus
RD
φ
Bus cycle A Bus cycle B
T
(b) Idle cycle inserted
1
T
2
T
3
T
i
i
T
) between bus
1
T
2