HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 438

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13. Smart Card Interface
13.3.4
Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described in this section.
Table 13.3 Smart Card Interface Register Settings
Register Address*
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Legend:
⎯:
Notes: 1. Lower 20 bits of the address in advanced mode.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card
interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the
direct convention type, or set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section
13.3.5, Clock.
Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 13.3.5, Clock, for
the method of calculating the value to be set.
Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial
communication functions. See section 12, Serial Communication Interface, for details. The CKE1
and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock
output, set these bits to 01. Clock output is performed when the GM bit is set to 1 in SMR. Clock
output can also be fixed low or high.
Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to
0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention
type. To use the smart card interface, set the SMIF bit to 1.
Rev.4.00 Aug. 20, 2007 Page 394 of 638
REJ09B0395-0400
Unused bit.
2. When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Register Settings
H'FFFB0
H'FFFB1
H'FFFB2
H'FFFB3
H'FFFB4
H'FFFB5
H'FFFB6
1
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
⎯
Bit 6
0
BRR6
RIE
TDR6
RDRF
RDR6
⎯
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
⎯
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
⎯
Bit
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
RDR2
SINV
TEND
CKS1
Bit 1
BRR1
CKE1*
TDR1
0
RDR1
⎯
2
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF