HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 349

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
1.
2.
3.
4.
Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
GRB
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
TP
TP
TP
The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are
output compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable
IMFA interrupts.
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits
G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in
NDRB.
The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change
from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
15
14
13
12
11
10
9
8
TCNT value
TCNT
95
00
95
65
05
Non-overlap margin
Non-Overlapping Pulse Output)
65
59
41
59
10. Programmable Timing Pattern Controller (TPC)
56
50
56
95
Rev.4.00 Aug. 20, 2007 Page 305 of 638
14
95
65
05
65
REJ09B0395-0400
Time