HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 498

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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17. Clock Pulse Generator
17.3
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
17.4
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
17.5
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
17.5.1
Table 17.4 summarizes the frequency division register.
Table 17.4 Frequency Division Register
Address*
H'EE01B
Note:
Rev.4.00 Aug. 20, 2007 Page 454 of 638
REJ09B0395-0400
* Lower 20 bits of the address in advanced mode.
Duty Adjustment Circuit
Prescalers
Frequency Divider
Register Configuration
Name
Division control register
Abbreviation
DIVCR
R/W
R/W
Initial Value
H'FC

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