HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 619

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HD6413008F

Manufacturer Part Number
HD6413008F
Description
Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3
8TCSR2
8TCSR3
Initial value
Read/Write
Initial value
Read/Write
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Bit
Bit
Compare match/input capture flag B
0
1
R/(W)*
R/(W)*
CMFB
CMFB
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
7
0
7
0
TCORB functions as an input capture register.
Compare match flag A
0
1
R/(W)*
R/(W)*
CMFA
CMFA
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
8TCNT = TCORA
6
0
6
0
Timer overflow flag
0
1
R/(W)*
R/(W)*
OVF
OVF
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
8TCNT overflows from H'FF to H'00.
5
0
5
0
Input capture enable
0
1
R/W
ICE
4
1
4
0
TCORB is a compare match register
TCORB is an input capture register
Output/input capture edge select B3 and B2
8TCSR3
ICE in
OIS3
OIS3
0
1
R/W
R/W
3
0
3
0
Rev.4.00 Aug. 20, 2007 Page 575 of 638
Bit 3
OIS3
0
1
0
1
Bit 1
H'FFF92
H'FFF93
Output select A1 and A0
OS1
OIS2
OIS2
R/W
R/W
0
1
2
0
2
0
Bit 2
OIS2
Bit 0
OS0
0
1
0
1
0
1
0
0
1
0
1
Appendix B Internal I/O Registers
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
OS1
OS1
R/W
R/W
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
1
0
1
0
Description
OS0
R/W
OS0
R/W
Description
0
0
0
0
8-bit timer channel 2
8-bit timer channel 3
REJ09B0395-0400

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