HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 179

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion) of CS
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of RD in the first read cycle and assertion of CS
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CS
bus cycle will overlap.
As long as RD and CS
non-insertion of an idle cycle can be specified.
Address bus
Data bus
HWR
RD
n
φ
may occur simultaneously. Figure 6.20 shows an example of the operation in
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
n
T
Long buffer-off time
do not change simultaneously, or if there is no problem even if they do,
1
T
2
T
3
T
1
T
2
Data collision
Address bus
Data bus
Rev.4.00 Aug. 20, 2007 Page 135 of 638
HWR
RD
φ
(b) Idle cycle inserted
Bus cycle A Bus cycle B
T
1
n
n
low output in the following
T
in the following bus cycle
2
T
3
T
REJ09B0395-0400
6. Bus Controller
i
T
1
T
2