HD6413008F RENESAS [Renesas Technology Corp], HD6413008F Datasheet - Page 92

• Manufacturer Part Number: HD6413008F
• Description: Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2. CPU
2.8.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority
High
Low
Note:
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
Rev.4.00 Aug. 20, 2007 Page 48 of 638
REJ09B0395-0400
Exception
sources
* Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
Exception-Handling State
Type of Exception
Reset
Interrupt
Trap instruction
or immediately after reset exception handling.
Reset
Interrupt
Trap instruction
Figure 2.12 Classification of Exception Sources
Detection Timing
Synchronized with clock
End of instruction
execution or end of
exception handling*
When TRAPA
instruction is executed
External interrupts
Internal interrupts (from on-chip supporting modules)
Start of Exception Handling
Exception handling starts immediately
when RES changes from low to high
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed