SE97 NXP [NXP Semiconductors], SE97 Datasheet - Page 19

• Manufacturer Part Number: SE97
• Description: DDR memory module temp sensor with integrated SPD, 3.3 V
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 6.
Instructions with R/W bit = 0.
SE97_5
Product data sheet
Status
Permanently
protected
Protected with
RWP
Not protected
Fig 17. Software Write Protect (read)
(1) Refer to
SDA
X = Don’t Care
Acknowledge when writing data or defining write protection
7.10.2.1 Permanent Write Protection (PWP)
7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP)
START condition
S
Table 7
0
Instruction
PWP, RWP or CRWP
page or byte write in
lower 128 bytes
RWP
CRWP
PWP
page or byte write in
lower 128 bytes
PWP or RWP
CRWP
page or byte write
slave address (memory)
1
If the software write-protection has been set with the PWP instruction, the first 128 bytes
of the memory are permanently write-protected. This write-protection cannot be cleared
by any instruction, or by power-cycling the device. Also, once the PWP instruction has
been successfully executed, the device no longer acknowledges any instruction (with 4-bit
fixed address of 0110b) to access the write-protection settings.
If the software write-protection has been set with the RWP instruction, it can be cleared
again with a CRWP instruction.
The two instructions, RWP and CRWP have the same format as a Byte Write instruction,
but with a different setting for the hardware address pins (as shown in
Byte Write instruction, it is followed by an address byte and a data byte, but in this case
the contents are all ‘Don’t Care’
must be applied on the A0 pin, and specific logical levels must be applied on the other two
(A1 and A2), as shown in
regarding the exact state of the acknowledge bit.
1
0
A2 A1 A0
R/W acknowledge
1
ACK
NACK
ACK
NACK
ACK
ACK
ACK
ACK
ACK
ACK
A
from slave
X
Rev. 05 — 6 August 2009
DDR memory module temp sensor with integrated SPD, 3.3 V
X
Table
dummy byte address
Address
not significant
address
not significant
not significant
not significant
address
not significant
not significant
address
X
(1)
X
5.
(Figure
X
no acknowledge
X
16). Another difference is that the voltage, V
X
from slave
ACK
NACK
ACK
NACK
ACK
ACK
ACK
ACK
ACK
ACK
X
(1)
A
X
Data byte
not significant
data
not significant
not significant
not significant
data
not significant
not significant
data
X
X
dummy data
X
X
no acknowledge
X
STOP condition
ACK
NACK
NACK
NACK
ACK
ACK
NACK
ACK
ACK
ACK
X
from slave
Table
© NXP B.V. 2009. All rights reserved.
X
002aac644
(1)
A
5). Like the
Write cycle
(T
no
no
no
yes
yes
no
yes
no
yes
P
SE97
cy(W)
19 of 54
)
I(ov)
,