SE97 NXP [NXP Semiconductors], SE97 Datasheet - Page 9

• Manufacturer Part Number: SE97
• Description: DDR memory module temp sensor with integrated SPD, 3.3 V
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SE97_5
Product data sheet
7.3.2.1 Alarm window
7.3.2.2 Critical trip
7.3.2 EVENT thresholds
The device provides a comparison window with an UPPER trip point and a LOWER trip
point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower
Boundary Alarm Trip register (03h). The Upper Boundary Alarm Trip register holds the
upper temperature trip point, while the Lower Boundary Alarm Trip register holds the lower
temperature trip point as modified by hysteresis as programmed in the Configuration
register. When enabled, the EVENT output triggers whenever entering or exiting (crossing
above or below) the alarm window.
The Upper Boundary Alarm Trip should always be set above the Lower Boundary Alarm
Trip.
The T
modified by hysteresis as programmed in the Configuration register. When the
temperature reaches the critical temperature value in this register (and EVENT is
enabled), the EVENT output asserts and cannot be de-asserted until the temperature
drops below the critical temperature threshold. The Event cannot be cleared through the
Clear EVENT bit (CEVNT) or SMBus Alert.
The Critical Alarm Trip should always be set above the Upper Boundary Alarm Trip.
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Advisory note:
– NXP Device: The EVENT output can be cleared through the Clear EVENT bit
– Competitor Device: The EVENT output can be cleared only through the
– Work-around: Only clear EVENT output using the Clear EVENT bit (CEVNT).
– There will be no change to NXP devices.
Advisory note:
– NXP device: Requires one conversion cycle (125 ms) after setting the alarm
– Competitor devices: Compares the alarm limit with temperature register at any
– Work-around: Wait at least 125 ms before enabling EVENT output (EOCTL = 1).
– SE97B will compare alarm window and temperature register immediately.
Advisory note:
– NXP device: Requires one conversion cycle (125 ms) after setting the Alarm
th(crit)
(CEVNT) or SMBus Alert.
Clear EVENT bit (CEVNT).
window before comparing the alarm limit with temperature register to ensure that
there is correct data in the temperature register before comparing with the Alarm
Window and operating EVENT output.
time, so they get the EVENT output immediately when new UPPER or LOWER
Alarm Windows and the EVENT output are set at the same time.
Window before comparing the alarm limit with temperature register to ensure that
there is correct data in the temperature register before comparing with the Alarm
Window and operating EVENT output.
temperature setting is programmed in the Critical Alarm Trip register (04h) as
Rev. 05 — 6 August 2009
DDR memory module temp sensor with integrated SPD, 3.3 V
© NXP B.V. 2009. All rights reserved.
SE97
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