PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 117

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
OCOL_INT[4:1]
RP_INT
If the OCOL_INT[x] bit is a logic one, an interrupt has been generated from a collision on the
associated outgoing bus. A collision is detected when ODETECT[x] is sampled high during
the same clock cycle that the OACTIVE[x] is set high. These interrupts are enabled with the
OCOLE[4:1] bits in the SBS Interrupt Enable register. These interrupt bits will be cleared
when read.
If the RP_INT is a logic one, an interrupt has been generated from a parity error on the
associated receive bus. This in an indication that there may be hardware or configuration
problem on the receive bus. This interrupt is enabled with the RPE bit in the SBS Interrupt
Enable register. This interrupt bit will be cleared when read.
SBS Telecom Standard Product Data Sheet
Preliminary
117