PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 236

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
RX_FI_BUSY
RX_MSG_LVL[3:0]
HDR_CRC_ERR
CRC_ERR
This bit indicates that the internal hardware is transferring data from the Receive FIFO RAM
into the Receive FIFO registers. The bit is set following a write to this register with the
RX_XFER_SYNC bit set or following a read from the PILC Receive FIFO Data Low
register.
Following an RX_XFER_SYNC write this bit need not be read by software if the time
interval to the successive Receive FIFO DATA register read is greater than approximately 5
SYSCLK cycles when FAST_RD_EN = ‘1’ or approximately 4 SYSCLK cycles when
FAST_RD_EN = ‘0’.
This bit need not be read by software if the time interval between successive Receive FIFO
DATA register reads greater than approximately 4 SYSCLK cycles when FAST_RD_EN =
‘1’ or approximately 3 SYSCLK cycles when FAST_RD_EN = ‘0’.
This means between a read access from the PILC Received FIFO Data Low register and a
read from the PILC Received FIFO Data High register. Note that there is no time restriction
between a read accesses from the PILC Received FIFO Data High register and a read from
the PILC Received FIFO Data Low register
This indicates the current number of messages in the Receive FIFO.
Values greater than 1000 will not occur.
If this bit is set to a logic one, the last message slot received was received with an errored
CRC-16 field. This bits is updated every message slot. This bit is provided as status only.
If this bit it set to ‘1’, the message at the head of the Receive FIFO has an errored CRC-16
field.
RX_MSG_LVL[3:0]
0000
:
1000
Number of Messages
0
:
8
SBS Telecom Standard Product Data Sheet
Preliminary
236