PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 317

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

14.10 Receive Serial LVDS Functional Timing
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Figure 42 below shows the relative timing of the receive LVDS links. In TelecomBus mode links
carry SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
tributary justification events and tributary alarm conditions are encoded in special control
characters. The upstream devices sourcing the links share a common clock and have a common
transport frame alignment that is synchronized by the Receive Serial Interface Frame Pulse signal
(RC1FP). Due to phase noise of clock multiplication circuits and backplane routing
discrepancies, the links will not be phase aligned to each other (within a tolerance level of 24 byte
times) but are frequency locked The delay from RC1FP being sampled high to the first and last
J0 character is shown in Figure 42. In this example, the first J0 is delivered by the working link
(RNWRK/RPWRK). The delay to the last J0 represents the time when both links have delivered
their J0 character. The minimum value for the internal programmable delay (RC1FPDLY[13:0])
is the delay to the last J0 character plus 15. The maximum value is the delay to the first J0
character plus 31. Consequently, the external system must ensure that the relative delays between
all the receive LVDS links be less than 16 bytes. The relative phases of the links in Figure 42 are
shown for illustrative purposes only.
Figure 42 Receive LVDS Link Timing
Figure 43 shows the timing relationships around the RC1FP signal. The Outgoing Memory Page
selection signal (OCMP) and the Receive Working Serial Data Select signal (RWSEL) are only
valid at the SYSCLK cycle located by RC1FP. They are ignored at all other locations within the
transport frame. The delay from RC1FP is to the J0 byte on the outgoing SBI or TelecomBus
stream is the sum of the value programmed into the RC1FPDLY[13:0] register and processing
delay of 18 SYSCLK cycles.
RNPROT/
RNWRK/
SYSCLK
RPPROT
RPWRK
RC1FP
...
...
Delay to First J0
Delay to Last J0
S3,3 / A2
S4,3 / A2
SBS Telecom Standard Product Data Sheet
S4,4 / A2
S1,1 / J0
S1,1 / J0
Preliminary
S2,1 / Z0
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