PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 326

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Symbol
tS
tS
tS
tH
tV
tS
tH
tH
tH
tV
Table 31 Microprocessor Interface Write Access (Figure 49)
Figure 49 Microprocessor Interface Write Timing
Notes on Microprocessor Interface Write Timing
1.
2.
3.
4.
5.
WR
AW
DW
ALW
ALW
L
LW
LW
DW
AW
(CSB+WRB)
A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
tH
Parameter tH
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4 V point of the clock.
ALW
D[7:0]
A[11:0]
ALE
, tV
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Write Set-up
Latch to Write Hold
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
L
, tS
AW
LW
is not applicable if address latching is used.
, and tH
tSalw
tVl
tVl
tSaw
LW
are not applicable.
tSlw
tHalw
tVwr
tVwr
tSdw
SBS Telecom Standard Product Data Sheet
VALID
tHaw
tHdw
Min
5
10
5
5
2
0
5
5
5
15
tHlw
Max
Preliminary
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALW
,
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