PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 26

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Description
The PM8610 SBI336 Bus Serializer (SBS) is a monolithic integrated circuit that implements
conversion between a byte-serial 19.44 MHz SBI bus or 77.76 MHz SBI336 bus and a redundant
777.6 Mbit/s bit-serial 8B/10B-base SBI336S bus.
In TelecomBus mode, the SBS implements conversion between any 19.44 MHz TelecomBus or
77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial
TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input
DS0 to be output on any output DS0. The redundant 777.6 Mbit/s serial interfaces can be disabled
and a byte-wide SBI336 bus can be enabled in its place with all the DS0 level switching
capabilities.
The SBS can be used to connect and switch high density T1/E1 framer devices supporting an SBI
bus with link layer devices supporting an SBI bus over a serial backplane. Placing a PM8620 or
PM8621 Narrowband Switch Element (NSE) between the framer and link layer devices allows up
to 20 Gbit/s NxDS0 switches to be constructed.
In the ingress direction, the SBS connects an incoming SBI stream to a pair of redundant serial
SBI336S LVDS links through a DS0 memory switch. The incoming SBI bus can be either a
single 77.76 MHz SBI bus (SBI336) or four 19.44 MHz SBI buses (SBI). In TelecomBus mode
an incoming 77.76 MHz TelecomBus or four 19.44 MHz TelecomBuses that have the J1 path
fixed and all high order pointer justifications converted to tributary pointer justifications can be
switched through a VT granular switch to a pair of redundant serial LVDS TelecomBus format
links. The incoming data is encoded into an extended set of 8B/10B characters and transferred
onto two redundant 777.6 Mbit/s serial LVDS links. SBI or TelecomBus frame boundaries,
pointer justification events and master timing controls are marked by 8B/10B control characters.
Incoming SPEs may be optionally overwritten with the locally generated X
random bit sequence (PRBS) pattern for diagnosis of downstream equipment. The PRBS
processor is configurable to handle any combination of SPEs and can be inserted independently
into either of the redundant LVDS links. A DS0 memory switch provides arbitrary mapping of
streams on the incoming SBI bus stream(s) to the working and protect LVDS links. In
TelecomBus mode, a VT1.5/VT2 memory switch provides arbitrary mapping of tributaries on the
incoming TelecomBus stream(s) to the working and protect LVDS links. Multi-cast is supported.
In the egress direction, the SBS connects two independent 777.6 Mbit/s serial LVDS links to an
outgoing SBI Bus. Each link contains a constituent SBI336S stream. Bytes on the links are
carried as 8B/10B characters. The SBS decodes the characters into data and control signals for a
single 77.76 MHz SBI336 bus or four 19.44 MHz SBI buses. Alternatively the SBS decodes two
independent 777.6 Mbit/s TelecomBus formatted serial LVDS links characters into a single 77.76
MHz or quad 19.44 MHz TelecomBuses. A PRBS processor is provided to monitor the decoded
payload for the X
any combination of SPEs in the serial LVDS link. Data on the outgoing SBI bus stream(s) may
be sourced from either of the LVDS links.
An In-band signaling link over the serial LVDS links allows this device to be controlled by a
companion switching device, a Narrowband Switching Element, PM8620 NSE-20G. This link can
be used as communication link between a central processor and the local microprocessor.
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+ X
18
+ 1 pattern in each SPE. The PRBS processor is configurable to handle
SBS Telecom Standard Product Data Sheet
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+ X
18
+ 1 pseudo-
Preliminary
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