PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 86
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PM8610-BIAP
Manufacturer Part Number
PM8610-BIAP
Description
SBS Telecom Standard Product Data Sheet Preliminary
Manufacturer
PMC [PMC-Sierra, Inc]
Datasheet
1.PM8610-BIAP.pdf
(338 pages)
- Current page: 86 of 338
- Download datasheet (2Mb)
10.19 Microprocessor Interface
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
#Change in these bits (received side) will not be processed if the received message CRC-16
indicates an error.
Interrupts can be generated when CRC errors are detected or the USER or LINK bits change
state. There is no inherent flow control provided by the In-Band Link Controller. The attached
microprocessor is able to provide flow control via interrupts when the in-band message fifo
overflows and via the USER bits in the header.
As each message arrives, the CRC-16 and valid bit is checked; if the valid bit is not set the
message is discarded, if it fails the CRC check it is flagged as being in error and an interrupt is
generated if enabled. If the CRC-16 is OK, regardless of the valid bit, the Page Link, User and
Aux bits are passed on immediately. If the fifo erroneously overflows, an interrupt is generated.
The Microprocessor Interface block provides normal and test mode registers, and logic required
to connect to the microprocessor interface. The normal mode registers are required for normal
operation, and test mode registers are used to enhance testability of the SBS.
Aux[7:0]#
Address
000H
001H
002H
003H
004H
005H
006H
007H
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
User defined auxiliary register
indication.
Register
SBS Master Reset
SBS Master Configuration
SBS Revision/Part Number
SBS Part Number/Manufacturer ID
SBS Master Bypass
SBS Master SPE Control #1
SBS Master SPE Control #2
SBS Receive Synchronization Delay
SBS In-Band Link User Bits
SBS Receive Configuration
SBS Transmit Configuration
SBS Transmit J1 Configuration
SBS Transmit V1 Configuration
SBS Transmit H1-H2 Pointer Value
SBS Transmit Alternate H1-H2 Pointer Value
SBS Transmit H1-H2 Pointer Selection
SBS Master Interrupt Source
SBS Interrupt Register
SBS Interrupt Enable Register
SBS Loopback Configuration
SBS Telecom Standard Product Data Sheet
Transmitted immediately.
User defined auxiliary register
indication.
Transmitted immediately.
Preliminary
86
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