PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 45

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Pin Name
TJUST_REQ
TJUST_REQ
(continued)
Microprocessor Interface (30 Signals)
CSB
RDB
WRB
Type
Output
Input
Input
Input
Pin No.
D22
AB25
AA25
AA26
Transmit Justification Request (TJUST_REQ). This is the
transmit side justification request when configured for SBI336 byte-
wide interface instead of the Serial SBI336S interface and when
connecting to a link layer device. This signal is held low when
connecting to a SBI336 physical layer device or when in
TelecomBus mode.
The SBI336 Bus Justification Request signal, TJUST_REQ, is used
to speed up, slow down or maintain the minimal rate of a slave
timed SBI336 device.
This active high signal indicates negative timing adjustments on the
SBI336 bus when asserted high during the V3 or H3 octet,
depending on the tributary type. In response to this the slave timed
SBI336 device should send an extra byte in the V3 or H3 octet of
the next receive frame along with a valid payload signal indicating
a negative justification.
This signal indicates positive timing adjustments on the SBI336 bus
when asserted high during the octet following the V3 or H3 octet,
depending on the tributary type. The slave timed SBI336 device
should respond to this by not sending an octet during the V3 or H3
octet of the next receive frame along with a valid payload signal
indicating a positive justification.
For fractional rate links this signal is asserted high during any
available information byte to indicate to the slave timed SBI336
device that the timing master device is able to accept another byte
of data. For every byte that this signal is asserted high the slave
device is expected to send a valid byte of data.
All timing adjustments from the slave timed device in response to
the justification request must still set the payload and payload
indicators appropriately for timing adjustments.
TJUST_REQ is updated on the rising edge of SYSCLK.
Chip Select Bar. The active low chip select signal (CSB) controls
microprocessor access to registers in the SBS device. CSB is set
low during SBS Microprocessor Interface Port register accesses.
CSB is set high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled using RDB
and WRB signals only), CSB should be connected to an inverted
version of the RSTB input.
Read Enable Bar. The active low read enable bar signal (RDB)
controls microprocessor read accesses to registers in the SBS
device. RDB is set low and CSB is also set low during SBS
Microprocessor Interface Port register read accesses. The SBS
drives the D[15:0] bus with the contents of the addressed register
while RDB and CSB are low.
Write Enable Bar. The active low write enable bar signal (WRB)
controls microprocessor write accesses to registers in the SBS
device. WRB is set low and CSB is also set low during SBS
Microprocessor Interface Port register write accesses. The
contents of D[15:0] are clocked into the addressed register on the
rising edge of WRB while CSB is low.
Function
SBS Telecom Standard Product Data Sheet
Preliminary
45