PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 73

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

10.3
10.4
10.4.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
CAS Expanders
The Channel Associated Signaling Expander blocks, ICASE and OCASE, pull the CAS
information from the SBI336 formatted bus on a tributary basis so that it can be switched through
the memory switch with the DS0 data. For tributaries enabled for DS0 switching the Channel
Associated Signaling bits (CAS bits) are double buffered on a signaling multiframe boundary and
repeated along side the tributary data for the duration of the multiframe. This function is enabled
on a per tributary basis and can be used for T1 and E1 tributaries simultaneously across SBI
SPEs. This block adds one T1 multiframe (24 frames) or one E1 multiframe (16 frames) of
latency to the CAS bits.
Memory Switch Units
The Memory Switch Unit blocks, IMSU and OMSU, provide DS0 or column switching of the
SBI336 or 77.76 MHz TelecomBus. Any input byte (or column) can be switched to any output
byte (or column). Four bits of Channel Associated Signaling (CAS) and three or four bits of
control information are switched along with the data byte. In SBI336 mode, the control signals
are PL, V5 and JUST_REQ. In TelecomBus mode, the control signals are PL, TPL, V5 and
TAIS.
In DS0 switch mode, the data entering the MSU is stored in two alternating pages of memory.
Each page contains one complete frame (9720 bytes) of data. One of these alternating pages is
currently filling while the other is currently full. Data exiting the MSU is extracted from the
currently full page. As a consequence, the MSU imposes a nominal switching latency of 1
frame (125us). The selection of bytes to fill each output port requires a switching connection
memory. Control is required for each of the 9720 bytes in the output SBI336 frame. Complete
specification of an output byte requires 14 bits to specify which of the 9720 input bytes to use.
Dual copies of this control memory are required to provide hitless frame boundary switchover.
In column switch mode, the same switching principle described above is used, but less memory is
required. Data entering the MSU is stored in two alternating pages of memory. Each page
contains one row (1080 bytes) of data. In this mode, the nominal latency is 1 row if a frame (<15
us). The switching connection memory for the output port requires control for each of the 1080
columns in the frame. Complete specification of an output column requires 11 bits to specify
which of the 1080 input columns to use. Dual copies of this control memory are required to
provide hitless frame boundary switchover.
Each MSU can be independently bypassed for reduced latency or debugging purposes.
The Data Buffer block contains a double buffer structure for each frame consisting of a data byte,
4-bits of Channel Associated Signaling information and 4 bits of control information necessary
for identifying valid data and timing.
Data Buffer
SBS Telecom Standard Product Data Sheet
Preliminary
73