PM8610-BIAP PMC [PMC-Sierra, Inc], PM8610-BIAP Datasheet - Page 129

• Manufacturer Part Number: PM8610-BIAP
• Description: SBS Telecom Standard Product Data Sheet Preliminary
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000168, Issue 3
Register 020H: ISTA Incoming Parity Configuration
IPE[4:1]
INCLIPL[4:1]
INCLIC1[4:1]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The incoming parity interrupt enable bits (IPE[4:1]) are active high interrupt enables. When
IPE[x] is set to a logic one, the occurrence of a parity error on the incoming bus will cause an
interrupt to be asserted on the INTB output. When IPE is set to a logic zero, incoming parity
errors will not cause and interrupt. IPE[4:2] are only valid when in 19 MHz mode.
The INCLIPL bits control whether the IPL[x] input signal participates in the incoming parity
calculations. When INCLIPL[x] is set to a logic one, the parity signal includes the IPL[x]
input. When INCLIPL[x] is set to a logic zero, parity is calculated without regard to the state
of IPL[x]. These bits only take effect when in TelecomBus mode. INCLIPL[4:2] are only
valid when in 19 MHz mode.
The INCLIC1 bits control whether the IC1FP input signal participates in the incoming parity
calculations. When INCLIC1[x] is set to a logic one, the parity signal includes the IC1FP
input. When INCLIC1[x] is set to a logic zero, parity is calculated without regard to the state
of IC1FP. These bits only take effect when in TelecomBus mode. INCLIC1[4:2] are only
valid when in 19 MHz mode.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INCLIC1[2]
INCLIC1[1]
INCLIPL[4]
INCLIPL[3]
INCLIPL[2]
INCLIPL[1]
Function
IPE[4]
IPE[3]
IPE[2]
IPE[1]
INCLIC1[4]
INCLIC1[3]
IOP[4]
IOP[3]
IOP[2]
IOP[1]
SBS Telecom Standard Product Data Sheet
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Preliminary
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