DV164136 Microchip Technology, DV164136 Datasheet - Page 135

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-6:
© 2009 Microchip Technology Inc.
RB0/INT0/FLT0
RB1/INT1/
PMA4
RB2/INT2/
PMA3
RB3/INT3/
PMA2/ECCP2/
P2A
RB4/KBI0/
PMA1
RB5/KBI1/
PMA0
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only). Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD is enabled.
ECCP2
Function
PORTB FUNCTIONS
P2A
PMA4
PMA3
PMA2
PMA1
PMA0
INT0
FLT0
INT1
INT2
INT3
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
(1)
(1)
Setting
TRIS
0
1
1
1
0
1
1
x
0
1
1
x
0
1
1
x
0
1
0
0
1
x
0
1
x
0
1
1
x
0
1
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
External interrupt 0 input.
Enhanced PWM Fault input (ECCP1 module); enabled in software.
LATB<1> data output.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
External interrupt 1 input.
Parallel Master Port address out.
LATB<2> data output.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
External interrupt 2 input.
Parallel Master Port address out.
LATB<3> data output.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
External interrupt 3 input.
Parallel Master Port address out.
ECCP2 compare output and CCP2 PWM output; takes priority over port
data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
LATB<4> data output.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Parallel Master Port address out.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Parallel Master Port address out.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
PIC18F87J11 FAMILY
Description
DS39778D-page 135
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