DV164136 Microchip Technology, DV164136 Datasheet - Page 200

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
17.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.1
The user must configure the CCP pin as an output by
clearing the appropriate TRIS bit.
FIGURE 17-3:
DS39778D-page 200
the I/O latch)
Compare Mode
CCP PIN CONFIGURATION
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR5H
CCPR4H
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR5L
CCPR4L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP4IF
T3CCP2
Set CCP5IF
17.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
17.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCP
pin is not affected. Only a CCP interrupt is generated,
if enabled, and the CCPxIE bit is set.
Note:
CCP4CON<3:0>
CCP5CON<3:0>
Output
Output
Logic
4
Logic
4
Clearing the CCP5CON register will force
the RG4 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
S
R
S
R
Q
Q
© 2009 Microchip Technology Inc.
Output Enable
Output Enable
TRIS
TRIS
CCP4 pin
CCP5 pin