DV164136 Microchip Technology, DV164136 Datasheet - Page 147

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-16: PORTG FUNCTIONS
© 2009 Microchip Technology Inc.
RG0/PMA8/
ECCP3/P3A
RG1/PMA7/
TX2/CK2
RG2/PMA6/
RX2/DT2
RG3/PMCS1/
CCP4/P3D
RG4/PMCS2/
CCP5/P1D
Legend:
Pin Name
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
ECCP3
PMCS1
PMCS2
PMA8
PMA7
PMA6
CCP4
CCP5
RG0
RG1
RG2
RG3
RG4
P3A
TX2
CK2
RX2
DT2
P3D
P1D
Setting
TRIS
0
1
x
0
0
1
x
1
1
1
0
1
x
1
1
1
0
1
x
x
0
1
0
0
1
x
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ECCP3 compare and PWM output; takes priority over port data.
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Parallel Master Port address.
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<2> data output.
Parallel Master Port address.
Asynchronous serial receive data input (EUSART2 module).
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<3> data output.
PORTG<3> data input.
Parallel Master Port address chip select 1
Parallel Master Port address chip select 1 in.
CCP4 compare output and CCP4 PWM output; takes priority over port data.
CCP4 capture input.
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<4> data output.
PORTG<4> data input.
Parallel Master Port address chip select 2
CCP5 compare output and CCP5 PWM output; takes priority over port data.
CCP5 capture input.
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<0> data output.
PORTG<0> data input.
Parallel Master Port address.
ECCP3 capture input.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial clock input (EUSART2 module).
PORTG<2> data input.
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PIC18F87J11 FAMILY
Description
DS39778D-page 147