DV164136 Microchip Technology, DV164136 Datasheet - Page 444

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
DS39778D-page 444
I
I
I
I
MSSP I
MSSP I
Parallel Master Port Read ........................................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port ................................................... 409
Parallel Slave Port Read .................................. 162, 165
Parallel Slave Port Write .................................. 162, 165
Program Memory Read ............................................ 405
Program Memory Write ............................................ 406
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
PWM Direction Change ........................................... 216
PWM Direction Change at Near 100% Duty Cycle .. 216
PWM Output ............................................................ 202
Read and Write, 8-Bit Data, Demultiplexed Address 169
Read, 16-Bit Data, Demultiplexed Address ............. 172
Read, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 171
Read, 8-Bit Data, Partially Multiplexed Address ...... 169
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
Repeated Start Condition ......................................... 258
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 286
Slave Synchronization ............................................. 229
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 228
SPI Mode (Slave Mode, CKE = 0) ........................... 230
SPI Mode (Slave Mode, CKE = 1) ........................... 230
Synchronous Reception (Master Mode, SREN) ...... 289
Synchronous Transmission ...................................... 287
Synchronous Transmission (Through TXEN) .......... 288
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 408
Transition for Entry to Idle Mode ................................ 48
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to PRI_RUN Mode . 46
Transition From SEC_RUN Mode to PRI_RUN Mode
Transition to RC_RUN Mode ..................................... 46
Write, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
2
2
2
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 250
C Slave Mode (7-Bit Transmission) ....................... 244
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ........ 263
10-Bit Addressing Mode) ................................. 252
abled) ............................................................... 219
abled) ............................................................... 219
Address ............................................................ 174
dress ................................................................ 173
Strobe .............................................................. 171
plexed Address ................................................ 170
(OST) and Power-up Timer (PWRT) ................ 407
V
V
V
326
(HSPLL) ............................................................. 45
............................................................................ 55
DD
DD
DD
2
2
C Bus Data ................................................. 419
C Bus Start/Stop Bits ................................. 419
), Case 1 ...................................................... 54
), Case 2 ...................................................... 55
Rise < T
PWRT
) ............................................ 54
DD
, V
DD
Rise > T
PWRT
DD
)
,
Timing Diagrams and Specifications
TSTFSZ ........................................................................... 371
Two-Speed Start-up ................................................. 315, 326
Two-Word Instructions
TXSTAx Register
V
V
Voltage Reference Specifications .................................... 399
Voltage Regulator (On-Chip) ........................................... 325
W
Watchdog Timer (WDT) ........................................... 315, 323
WCOL ...................................................... 257, 258, 259, 262
WCOL Status Flag ................................... 257, 258, 259, 262
WWW Address ................................................................ 433
WWW, On-Line Support ...................................................... 7
DDCORE
Write, 16-Bit Muliplexed Data, Partially Multiplexed Ad-
Write, 8-Bit Data, Demultiplexed Address ............... 172
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 172
Write, 8-Bit Data, Partially Multiplexed Address ...... 170
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
Capture/Compare/PWM Requirements (Including ECCP
CLKO and I/O Requirements ........................... 404, 405
EUSART Synchronous Receive Requirements ....... 421
EUSART Synchronous Transmission Requirements ....
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Slave Mode, CKE =
Example SPI Slave Mode Requirements (CKE = 1) 416
External Clock Requirements .................................. 402
I
I
Internal RC Accuracy (INTOSC, INTRC Sources) ... 403
MSSP I
MSSP I
Parallel Master Port Read Requirements ................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port Requirements ............................ 409
PLL Clock ................................................................ 403
Program Memory Write Requirements .................... 406
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Timer0 and Timer1 External Clock Requirements ... 408
Example Cases .......................................................... 71
BRGH Bit ................................................................. 275
Operation in Sleep Mode ......................................... 326
Power-up Requirements .......................................... 326
Associated Registers ............................................... 324
Control Register ....................................................... 323
During Oscillator Failure .......................................... 327
Programming Considerations .................................. 323
2
2
C Bus Data Requirements (Slave Mode) .............. 418
C Bus Start/Stop Bits Requirements (Slave Mode) .....
/V
Address ........................................................... 174
dress ................................................................ 173
Strobe .............................................................. 171
plexed Address ................................................ 170
Modules) .......................................................... 412
421
0) ..................................................................... 413
1) ..................................................................... 414
0) ..................................................................... 415
417
(OST), Power-up Timer (PWRT) and Brown-out
Reset ............................................................... 407
CAP
2
2
C Bus Data Requirements ......................... 420
C Bus Start/Stop Bits Requirements .......... 419
Pin .......................................................... 325
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