DV164136 Microchip Technology, DV164136 Datasheet - Page 327

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.1
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including
Section 3.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
24.5
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 24-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor
(CM) latch. The CM is set on the falling edge of the
device clock source but cleared on the rising edge of
the sample clock.
FIGURE 24-4:
© 2009 Microchip Technology Inc.
Peripheral
Source
INTRC
(32 μs)
Clock
Fail-Safe Clock Monitor
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
serial
(2.048 ms)
488 Hz
÷ 64
SLEEP
FSCM BLOCK DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
instructions
C
S
Q
Q
(refer
Detected
Failure
Clock
to
PIC18F87J11 FAMILY
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 24-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
• the device clock source is switched to the internal
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 24.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
24.5.1
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
fail-safe clock events also reset the WDT and post-
scaler, allowing it to start timing from when execution
speed was changed and decreasing the likelihood of
an erroneous time-out.
setting bit OSCFIF (PIR2<7>);
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
FSCM AND THE WATCHDOG TIMER
DS39778D-page 327