DV164136 Microchip Technology, DV164136 Datasheet - Page 270

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
TABLE 19-4:
DS39778D-page 270
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1MSK
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2MSK
SSP2CON1
SSP2CON2
SSP2STAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
2:
(1)
(1)
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
Slave operating modes in 7-bit Masking mode. See Section 19.4.3.4 “7-Bit Address Masking Mode” for
more details.
Alternate bit definitions for use in I
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP1 Baud Rate Reload Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
MSSP2 Baud Rate Reload Register (I
GIE/GIEH PEIE/GIEL
OSCFIF
OSCFIE
OSCFIP
SSP2IE
SSP2IP
TRISC7
TRISD7
SSP2IF
PMPIE
PMPIP
PMPIF
WCOL
WCOL
GCEN
GCEN
GCEN
GCEN
MSK7
MSK7
Bit 7
SMP
SMP
REGISTERS ASSOCIATED WITH I
ACKSTAT
ACKSTAT ADMSK5
ACKSTAT
ACKSTAT ADMSK5
TRISC6
TRISD6
BCL2IF
BCL2IE
BCL2IP
SSPOV
SSPOV
CM2IF
CM2IE
CM2IP
MSK6
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
CKE
TMR0IE
TRISC5
TRISD5
SSPEN
ACKDT
SSPEN
ACKDT
CM1IF
CM1IE
CM1IP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
MSK5
MSK5
Bit 5
D/A
D/A
2
2
C™ Slave mode),
C Slave mode),
2
C Slave mode operations only.
(2)
(2)
ADMSK4
ADMSK4
TRISC4
TRISD4
ACKEN
ACKEN
INT0IE
2
2
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
MSK4
MSK4
C Master mode)
C Master mode)
Bit 4
CKP
CKP
—
—
—
P
P
2
(2)
(2)
C™ OPERATION
ADMSK3
ADMSK3
TMR4IF
TMR4IE
TMR4IP
SSP1IE
SSP1IP
TRISC3
TRISD3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
SSPM3
SSPM3
RCEN
RCEN
MSK3
MSK3
RBIE
Bit 3
S
S
(2)
(2)
ADMSK2
ADMSK2
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
CCP1IF
CCP5IF
TRISC2
TRISD2
SSPM2
SSPM2
LVDIE
LVDIP
LVDIF
MSK2
MSK2
Bit 2
PEN
PEN
R/W
R/W
(2)
(2)
ADMSK1
ADMSK1
© 2009 Microchip Technology Inc.
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IE
CCP4IP
CCP4IF
TRISC1
TRISD1
SSPM1
SSPM1
INT0IF
MSK1
RSEN
MSK1
RSEN
Bit 1
UA
UA
2
(2)
(2)
C™ mode.
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISD0
SSPM0
SSPM0
MSK0
MSK0
RBIF
Bit 0
SEN
SEN
SEN
SEN
BF
BF
on Page:
2
Values
C™
Reset
60
60
60
60
60
60
58
58
58
61
61
61
57
60
60
60
60
60
58
58
58
61
61
61