DV164136 Microchip Technology, DV164136 Datasheet - Page 141

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.6
PORTE is an 8-bit wide, bidirectional port. All pins on
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
© 2009 Microchip Technology Inc.
Note:
PORTE, TRISE and
LATE Registers
These pins are configured as digital inputs
on any device Reset.
PIC18F87J11 FAMILY
PORTE is also multiplexed with Enhanced PWM
outputs B and C for ECCP1 and ECCP3 and outputs B,
C and D for ECCP2. For all devices, their default
assignments are on PORTE<6:0>. On 80-pin devices,
the multiplexing for the outputs of ECCP1 and ECCP3
is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For devices operating in Microcontroller mode, pin RE7
can be configured as the alternate peripheral pin for the
ECCP2 module and Enhanced PWM output 2A. This is
done by clearing the CCP2MX Configuration bit.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals PMWR and
PMRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, refer to Section 2.6 “Reference Clock
Output”.
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
INITIALIZING PORTE
DS39778D-page 141