DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet
DEMO9S08EL32
Specifications of DEMO9S08EL32
Related parts for DEMO9S08EL32
DEMO9S08EL32 Summary of contents
Page 1
MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 Data Sheet HCS08 Microcontrollers MC9S08EL32 Rev. 3 7/2008 freescale.com ...
Page 2
...
Page 3
MC9S08EL32 Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage ...
Page 4
...
Page 5
... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. MC9S08EL32 Data Sheet Covers MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 MC9S08EL32 Rev. 3 7/2008 ...
Page 6
... The following revision history table summarizes changes contained in this document. Revision Revision Number Date 3 07/2008 Initial public revision © Freescale Semiconductor, Inc., 2008. All rights reserved. This product incorporates SuperFlash MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Description of Changes ® Technology licensed from SST. Freescale Semiconductor ...
Page 7
... Serial Communications Interface (S08SCIV4)..................... 249 Chapter 15 Real-Time Counter (S08RTCV1) ........................................... 269 Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) ......................... 279 Chapter 17 Development Support ........................................................... 307 Appendix A Electrical Characteristics...................................................... 331 Appendix B Ordering Information and Mechanical Drawings................ 355 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 7 ...
Page 8
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 9
... FLASH and EEPROM ....................................................................................................................47 4.5.1 Features .............................................................................................................................47 4.5.2 Program and Erase Times .................................................................................................47 4.5.3 Program and Erase Command Execution .........................................................................48 4.5.4 Burst Program Execution ..................................................................................................49 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 ...
Page 10
... Edge and Level Sensitivity ...............................................................................................81 6.3.3 Pull-up/Pull-down Resistors .............................................................................................82 6.3.4 Pin Interrupt Initialization .................................................................................................82 6.4 Pin Behavior in Stop Modes ............................................................................................................82 6.5 Parallel I/O and Pin Control Registers ............................................................................................82 6.5.1 Port A Registers ................................................................................................................83 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Title Chapter 5 Chapter 6 Parallel Input/Output Control Page Freescale Semiconductor ...
Page 11
... ICS Control Register 1 (ICSC1) .....................................................................................120 8.3.2 ICS Control Register 2 (ICSC2) .....................................................................................121 8.3.3 ICS Trim Register (ICSTRM) .........................................................................................122 8.3.4 ICS Status and Control (ICSSC) .....................................................................................122 8.4 Functional Description ..................................................................................................................123 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Title Chapter 7 Chapter 8 Page 11 ...
Page 12
... Data Result High Register (ADCRH) .............................................................................146 10.3.4 Data Result Low Register (ADCRL) ..............................................................................146 10.3.5 Compare Value High Register (ADCCVH) ....................................................................147 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Title Chapter 9 Chapter 10 ) ..................................................................................................143 DDAD ) .................................................................................................143 SSAD ) ...................................................................................143 REFH ) ....................................................................................143 REFL Page Freescale Semiconductor ...
Page 13
... IIC Data I/O Register (IICD) ..........................................................................................173 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................174 11.4 Functional Description ..................................................................................................................175 11.4.1 IIC Protocol .....................................................................................................................175 11.4.2 10-bit Address .................................................................................................................178 11.4.3 General Call Address ......................................................................................................179 11.5 Resets ............................................................................................................................................179 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Title Chapter 11 Page 13 ...
Page 14
... IMSG to Minimize Interrupts .........................................................................218 12.6.11Sleep and Wakeup Operation ..........................................................................................219 12.6.12Polling Operation ............................................................................................................219 12.6.13LIN Data Integrity Checking Methods ...........................................................................219 12.6.14High-Speed LIN Operation .............................................................................................220 12.6.15Bit Error Detection and Physical Layer Delay ...............................................................223 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Title Chapter 12 Page Freescale Semiconductor ...
Page 15
... SCI Control Register 2 (SCIxC2) ...................................................................................256 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................257 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................259 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................260 14.2.7 SCI Data Register (SCIxD) .............................................................................................261 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Title Chapter 13 Chapter 14 Page 15 ...
Page 16
... TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................293 16.4 Functional Description ..................................................................................................................294 16.4.1 Counter ............................................................................................................................295 16.4.2 Channel Mode Selection .................................................................................................297 16.5 Reset Overview .............................................................................................................................300 16.5.1 General ............................................................................................................................300 16.5.2 Description of Reset Operation .......................................................................................300 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Title Chapter 15 Chapter 16 Page Freescale Semiconductor ...
Page 17
... A.9 Internal Clock Source (ICS) Characteristics .................................................................................342 A.10 Analog Comparator (ACMP) Electricals ......................................................................................343 A.11 ADC Characteristics ......................................................................................................................344 A.12 AC Characteristics .........................................................................................................................347 A.12.1 Control Timing ...............................................................................................................347 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Title Chapter 17 Development Support Appendix A Electrical Characteristics ...
Page 18
... A.14 EMC Performance .........................................................................................................................353 A.14.1 Radiated Emissions .........................................................................................................353 A.14.2 Conducted Transient Susceptibility ................................................................................354 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................355 B.1.1 Device Numbering Scheme ............................................................................................355 B.2 Mechanical Drawings ....................................................................................................................356 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Title Appendix B Page Freescale Semiconductor ...
Page 19
... Package type TSSOP Port Interrupts ACMP1 ACMP2 yes ADC channels DBG ICS IIC RTC SCI SLIC SPI TPM1 channels TPM2 channels XOSC MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor t 9S08EL32 9S08EL16 32768 16384 1024 512 TSSOP TSSOP TSSOP ...
Page 20
... ANALOG-TO-DIGITAL 16 CONVERTER (ADC) is internally connected to V and internally connected SSA REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 . SS Freescale Semiconductor ...
Page 21
... REFL = Not bonded to pins in 20-pin package = In 20-pin packages DDA REFH Figure 1-2. MC9S08SL16 and MC9S08SL8 Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor shows the structure of the MC9S08SL16 Series. ANALOG COMPARATOR + (ACMP1) – OUT TCLK 2-CHANNEL TIMER/PWM ...
Page 22
... Serial Peripheral Interface Serial Communications Interface Real-Time Counter Timer Pulse Width Modulator On-Chip ICE Debug MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Table 1-2. Module Versions Module (CPU) (ICS) (ACMP_5V) (ADC) (IIC) (SLIC) (SPI) (SCI) (RTC) (TPM) (DBG) Version Freescale Semiconductor ...
Page 23
... XOSC CPU EXTAL XTAL * The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor TCLK TPM1 TPM2 COP RTC FFCLK* BDC Figure 1-3 ...
Page 24
... Chapter 1 Device Overview MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 25
... PTC5/PIC5/ACMP2O/ADP13 PTC4/PIC4/ADP12 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/PIC3/TPM1CH3/ADP11 PTC2/PIC2/TPM1CH2/ADP10 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/PIC3/TPM1CH3/ADP11 PTC2/PIC2/TPM1CH2/ADP10 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 1-1 for details PTC6/PIC6/ACMP2+/ADP14 27 2 PTC7/PIC7/ACMP2–/ADP15 26 RESET 3 PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 25 BKGD/MS 4 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 24 V ...
Page 26
... RESET PORT PORT DDA REFH SSA REFL Figure 2-3. Basic System Connections and V REFH REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO2 PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL pins are the voltage reference high and Freescale Semiconductor ...
Page 27
... The voltage measured on the internally-pulled-up RESET pin DD is not pulled the RESET pin is required to drive pullup. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor (S08ICSV2).” (when used) and should not be driven above V DD NOTE DD . The internal gates connected to this pin are pulled to ...
Page 28
... To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev NOTE Control.” NOTE Freescale Semiconductor ...
Page 29
... SCI pins can be repositioned using SCIPS in SOPT1, default reset locations are on PTB0 and PTB1. 7 TPM2CH0 pin can be repositioned using T2CH0PS in SOPT2, default reset locations are on PTA1 ACMP and ADC are both enabled, both will have access to the pin. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor <-- Lowest Priority Alt 1 Alt 2 PIC5 ...
Page 30
... Chapter 2 Pins and Connections MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 31
... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 31 ...
Page 32
... The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08EL32 Series and MC9S08SL16 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
Page 33
... Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 3-1. Stop Mode Selection PPDC x Stop modes disabled ...
Page 34
... Refer to Mode” and Section 3.6.1, “Stop3 Mode MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev ” for specific information on system behavior in stop modes. Table 3-1. Most is below the LVD DD Section 3.7, “Stop2 Freescale Semiconductor ...
Page 35
... RTC must be enabled, else in standby. 5 ERCLKEN and EREFSTEN must be set in ICSC2, else in standby. For high frequency range (RANGE in ICSC2 set), the LVD must be enabled in stop3. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 3-2. Stop Mode Behavior Mode Stop2 Off ...
Page 36
... Chapter 3 Modes of Operation MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 37
... FLASH 0xBFFF 32768 BYTES 0xC000 0xFFFF 0xFFFF MC9S08EL32 Figure 4-1. MC9S08EL32 Series and MC9S08SL16 Series Memory Map MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 128 BYTES 0x007F 0x0080 RAM 1024 BYTES ...
Page 38
... Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08EL32 Series and MC9S08SL16 Series. Vector addresses for excluded features are reserved. Address ...
Page 39
... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-4, the whole address in column one is shown in bold. In ...
Page 40
... ELS1B ELS1A ELS2B ELS2A ELS3B ELS3A Freescale Semiconductor Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 — — ACMOD0 ACMOD0 — ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 ...
Page 41
... TPM2SC TOF 0x0061 TPM2CNTH Bit 15 0x0062 TPM2CNTL Bit 7 0x0063 TPM2MODH Bit 15 0x0064 TPM2MODL Bit 7 0x0065 TPM2C0SC CH0F MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor — — — — — — RXEDGIE 0 SBR12 SBR6 SBR5 SBR4 SCISWAI RSRC M ...
Page 42
... WAKETX TXABRT IMSG SLCWCM BTM 0 BT11 BT10 BT9 BT3 BT2 BT1 DLC3 DLC2 DLC1 Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — SLCIE SLCE BT8 BT0 SLCF 0 DLC0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 ...
Page 43
... PTAPE7 0x1841 PTASE PTASE7 0x1842 PTADS PTADS7 0x1843 Reserved — 0x1844 PTASC 0 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers PIN COP ILOP COPT STOPE SCIPS COPW ...
Page 44
... PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 PTCDS2 PTCDS1 PTCDS0 — — — PTCIF PTCACK PTCIE PTCMOD PTCPS2 PTCPS1 PTCPS0 PTCES2 PTCES1 PTCES0 — — — — — — — — — Freescale Semiconductor Bit 0 — — — — — — — ...
Page 45
... FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 4-4, are located in the FLASH memory. These registers Table 4-4 ...
Page 46
... When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See description of the security feature. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev RAM ;point one past RAM ;SP<-(H:X-1) Section 4.5.9, “Security”, for a detailed Freescale Semiconductor ...
Page 47
... FCLK and as an absolute time for the case where t shown include overhead for the command state machine and enabling and disabling of program and erase voltages. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Section 4.5.11.1, “FLASH and EEPROM Clock Divider = 1/f . The times are shown as a number ...
Page 48
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 4 NOTE is a flowchart for executing all of the commands except for burst Time if FCLK = 200 kHz 45 μs 20 μ 100 ms 20 μs 1 Freescale Semiconductor ...
Page 49
... The next sequential address selects a byte on the same burst block as the current byte being programmed. A burst block in this FLASH memory consists of 64 bytes. A new burst block begins at each 64-byte address boundary. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor (1) WRITE TO FCDIV START ...
Page 50
... WRITE 1 TO FCBEF TO LAUNCH COMMAND (2) AND CLEAR FCBEF YES FPVIOL OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure 4-3. Burst Program Flowchart 4-3. (1) Required only once after reset. (2) Wait at least four bus cycles before checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
Page 51
... A flowchart to execute the sector erase abort operation is shown in SECTOR ERASE ABORT FLOW SECTOR ERASE COMPLETED MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor START 1 FCCF ? 0 WRITE TO FLASH TO BUFFER ADDRESS AND DATA ...
Page 52
... MCU is secured. (The background debug controller can do blank check and mass erase commands only when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev NOTE NOTE Freescale Semiconductor ...
Page 53
... Security is engaged or disengaged based on the state of two register bits (SEC[1:0]) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 4 Memory NVPROT)”. ...
Page 54
... Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC = 1:0. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 55
... R DIVLD PRDIV8 W Reset Unimplemented or Reserved Figure 4-5. FLASH and EEPROM Clock Divider Register (FCDIV) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 4-4 for the absolute address assignments for all FLASH and Chapter 4 Memory 2 1 DIV ...
Page 56
... Min, 6.7 μs Max) FCLK (Decimal) 12 192.3 kHz 49 200 kHz 39 200 kHz 19 200 kHz 9 200 kHz 4 200 kHz 0 200 kHz 0 150 kHz and Equation 4-2. Eqn. 4-1 Eqn. 4-2 5.2 μs 5 μs 5 μs 5 μs 5 μs 5 μs 5 μs 6.7 μs Freescale Semiconductor ...
Page 57
... FLASH. For more detailed information about security, refer to Section 4.5.9, “Security.” 1 SEC changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 5 4 EPGMOD Table 4-8 ...
Page 58
... Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev KEYACC Description Section 4.5. “Security.” Freescale Semiconductor ...
Page 59
... Table 0 FLASH Protect Open Bit — This bit determines the protected FLASH locations that cannot be erased or FPOP programmed. See Table EPS 0x3 0x2 0x1 0x0 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor FPS Description Table 4-12. 4-13. 4-13. ...
Page 60
... Memory Size Number of Sectors Protected ... 18 24K 48 25K 50 26K 52 27K 54 28K 56 29K 58 30K 60 31K 62 32K 64 Freescale Semiconductor ...
Page 61
... After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH or EEPROM array is not completely erased. 1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH or EEPROM array is completely erased (all 0xFFFF). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 62
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Section 4.5.3, “Program and Erase Command FCMD FCMD Equate File Label 0x05 0x20 mByteProg 0x25 mBurstProg 0x40 mSectorErase 0x41 mMassErase 0x47 mEraseAbort Table 4-15. All other command mBlank Freescale Semiconductor ...
Page 63
... Illegal address detect (ILAD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 5-2) 63 ...
Page 64
... Bus 1:0 Bus 1:1 Bus = 1 ms. See t RTI (SOPT1),” (SOPT2),” for additional COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles in the appendix Section RTI Freescale Semiconductor ...
Page 65
... ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 65 ...
Page 66
... ACCUMULATOR * 3 3 INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW ² ² TOWARD HIGHER ADDRESSES ² * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame 0 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
Page 67
... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 67 ...
Page 68
... CH3IE TPM1 channel 3 CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — LVWIE Low-voltage warning — — — Software interrupt COPT Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode — Illegal address Freescale Semiconductor ...
Page 69
... When a low voltage warning condition is detected and is configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt request will occur. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 69 ...
Page 70
... Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Chapter 4, “Memory,” of this data sheet for the absolute address Freescale Semiconductor ...
Page 71
... ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 COP ...
Page 72
... BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Table 5-3. SRS Register Field Descriptions Description Description Freescale Semiconductor BDFR 0 ...
Page 73
... IIC Pin Select— These write-once bits select the location of the SCL and SDA pins of the IIC module. IICPS 00 SDA on PTA2, SCL on PTA3. 01 SDA on PTB6, SCL on PTB7. 1x SDA on PTB2, SCL on PTB3. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control STOPE SCIPS 0 0 ...
Page 74
... TPM1CH0 Pin Select— This write-once bit selects the location of the TPM1CH0 pin of the TPM1 module. T1CH0PS 0 TPM1CH0 on PTA0. 1 TPM1CH0 on PTC0. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev ACIC T2CH1PS 0 0 Table 5-6. SOPT2 Register Field Descriptions Description T2CH0PS T1CH1PS Freescale Semiconductor 0 1 T1CH0PS 0 ...
Page 75
... Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08EL32 is hard coded to the value 0x013. See also ID bits in MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ...
Page 76
... ADC module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev LVWIE LVDRE LVDSE 0 1 transitions below the trip point or after reset and V Supply Description LVDE already below V Supply Freescale Semiconductor 0 BGBE 0 LVW ...
Page 77
... Table 5-11. LVD and LVW trip point typical values LVDV:LVWV 0:0 0:1 1:0 1:1 1 See Electrical Characteristics appendix for minimum and maximum values. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control PPDF 1 LVDV LVWV ...
Page 78
... Chapter 5 Resets, Interrupts, and General System Control MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 79
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 2-1. The peripheral modules have priority over the general-purpose NOTE Figure Chapter 2, “ ...
Page 80
... Because of this, the EMC emissions may be affected by enabling pins as high drive. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 81
... CPU. Clearing of PTxIF is accomplished by writing PTxACK in PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled port pin is asserted while attempting to clear by writing PTxACK. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Figure V DD ...
Page 82
... I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev Freescale Semiconductor ...
Page 83
... Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTADD[7:6] PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 3:0 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. PTADD[3:0] MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor PTAD3 0 0 Figure 6-3 ...
Page 84
... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 3:0 1 Output slew rate control enabled for port A bit n. PTASE[3:0] MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTAPE3 Description PTASE3 Description PTAPE2 PTAPE1 PTAPE0 PTASE2 PTASE1 PTASE0 Freescale Semiconductor ...
Page 85
... Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 86
... A pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTAPS3 Description PTAES3 Description PTAPS2 PTAPS1 PTAPS0 PTAES2 PTAES1 PTAES0 Freescale Semiconductor ...
Page 87
... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 5 4 PTBD5 PTBD4 PTBD3 ...
Page 88
... Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTBPE5 PTBPE4 PTBPE3 Description PTBSE5 PTBSE4 PTBSE3 Description PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 89
... Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor PTBDS5 PTBDS4 ...
Page 90
... A pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTBPS3 Description PTBES3 Description PTBPS2 PTBPS1 PTBPS0 PTBES2 PTBES1 PTBES0 Freescale Semiconductor ...
Page 91
... Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor PTCD5 PTCD4 ...
Page 92
... Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTCPE5 PTCPE4 PTCPE3 Description PTCSE5 PTCSE4 PTCSE3 Description PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 Freescale Semiconductor ...
Page 93
... Port C Detection Mode — PTCMOD (along with the PTCES bits) controls the detection mode of the port C PTCMOD interrupt pins. 0 Port C pins detect edges only. 1 Port C pins detect both edges and levels. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor PTCDS5 PTCDS4 ...
Page 94
... A pull-up device is connected to the associated pin interrupt and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin interrupt and detects rising edge/high level for interrupt generation. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev PTCPS5 PTCPS4 PTCPS3 Description PTCES5 PTCES4 PTCES3 Description PTCPS2 PTCPS1 PTCPS0 PTCES2 PTCES1 PTCES0 Freescale Semiconductor ...
Page 95
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
Page 96
... X. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers Freescale Semiconductor ...
Page 97
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) 97 ...
Page 98
... No carry out of bit 7 1 Carry out of bit 7 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description Freescale Semiconductor ...
Page 99
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) 99 ...
Page 100
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 100 Freescale Semiconductor ...
Page 101
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Resets, Interrupts, and System Configuration ...
Page 102
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 102 chapter for more details. Freescale Semiconductor ...
Page 103
... H:X ← (H:X) + (M) AND #opr8i AND opr8a AND opr16a AND oprx16,X Logical AND A ← (A) & (M) AND oprx8,X AND ,X AND oprx16,SP AND oprx8,SP MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Cyc-by-Cyc Object Code Details IMM DIR 3 ...
Page 104
... rpp prpp prpp – – rpp 3 F5 rfp pprpp 4 ff prpp Freescale Semiconductor Affect on CCR – ...
Page 105
... Branch if (A) = (M) CBEQX #opr8i,rel Branch if (X) = (M) CBEQ oprx8,X+,rel Branch if (A) = (M) CBEQ ,X+,rel Branch if (A) = (M) CBEQ oprx8,SP,rel Branch if (A) = (M) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Cyc-by-Cyc Object Code Details REL ppp REL ...
Page 106
... – – rfwpppp 4 rr fppp 4 rr fppp – – – – – – rfwpppp 6 rr rfwppp prfwpppp 5 dd rfwpp – – rfwpp 4 rfwp 6 ff prfwpp Freescale Semiconductor 1 – ...
Page 107
... LDX opr16a LDX oprx16,X Load X (Index Register Low) from Memory X ← (M) LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Cyc-by-Cyc Object Code Details INH 6 52 fffffp IMM ...
Page 108
... Freescale Semiconductor Affect on CCR – – ...
Page 109
... STHX opr8a Store H:X (Index Reg.) STHX opr16a (M:M + $0001) ← (H:X) STHX oprx8,SP Enable Interrupts: Stop Processing STOP Refer to MCU Documentation I bit ← 0; Stop Processing MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Object Code DIR 39 INH 49 INH 59 IX1 69 ...
Page 110
... Freescale Semiconductor ...
Page 111
... Concatenated with CCR Bits: V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Cyc-by-Cyc Object Code Details INH INH 2+ 8F fp... Addressing Modes: DIR ...
Page 112
... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...
Page 113
... DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 NEG 3 SP1 9E61 ...
Page 114
... Chapter 7 Central Processor Unit (S08CPUV3) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 114 Freescale Semiconductor ...
Page 115
... LVDE and LVDSE bits in the SPMSC1 register. Figure 8-1 shows the MC9S08EL32 block diagram with the ICS highlighted. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor NOTE Distribution”, for a detailed view of the 115 ...
Page 116
... ANALOG-TO-DIGITAL 16 CONVERTER (ADC) is internally connected to V and internally connected SSA REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 . SS Freescale Semiconductor ...
Page 117
... Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL Engaged Internal mode is automatically selected out of reset 8.1.3 Block Diagram Figure 8-2 is the ICS block diagram. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Internal Clock Source (S08ICSV2) 117 ...
Page 118
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 118 Block ERCLKEN EREFS EREFSTEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block l (FEI) (FEE) l (FBI) ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
Page 119
... R ICSC1 CLKS W R ICSC2 BDIV W R ICSTRM ICSSC W MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor l Low Power (FBILP) l (FBE) l Low Power (FBELP) Table 8-1. ICS Register Summary RDIV RANGE HGO LP TRIM 0 0 IREFST Internal Clock Source (S08ICSV2) ...
Page 120
... Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 120 5 4 RDIV 0 0 Figure 8-3. ICS Control Register 1 (ICSC1) Description IREFS IRCLKEN IREFSTEN Freescale Semiconductor 0 0 ...
Page 121
... ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 5 4 RANGE HGO ...
Page 122
... CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 122 TRIM Figure 8-5. ICS Trim Register (ICSTRM) Description IREFST Description CLKST OSCINIT FTRIM Freescale Semiconductor ...
Page 123
... FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Description IREFS=1 CLKS=00 FLL Engaged Internal (FEI) ...
Page 124
... In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 124 Freescale Semiconductor ...
Page 125
... After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The completion of the switch is shown by the IREFST bit. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Internal Clock Source (S08ICSV2) 125 ...
Page 126
... FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Overview chapter). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 126 chapter). Device Freescale Semiconductor ...
Page 127
... BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 • MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Internal Clock Source (S08ICSV2) 127 ...
Page 128
... Internal Clock Source (S08ICSV2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 128 Freescale Semiconductor ...
Page 129
... The ACMP1 module can be configured to connect the output of the analog comparator to TPM1 input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM1 module for channel 0. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor t 9S08EL32 9S08EL16 ...
Page 130
... ANALOG-TO-DIGITAL 16 CONVERTER (ADC) is internally connected to V and internally connected SSA REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 . SS Freescale Semiconductor ...
Page 131
... Stop2 or Stop1 mode, the ACMP module will be in the reset state. 9.1.4.3 ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Analog Comparator (S08ACMPV2) 131 ...
Page 132
... Reference ACMPx+ ACMPx- Figure 9-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 132 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control - Comparator Figure 9-2. ACMPx INTERRUPT REQUEST ACIE ACF ACOPE ACMPxO Freescale Semiconductor ...
Page 133
... ACMP registers.This section refers to registers and control bits only by their names . Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 9-2. Table 9-2. Signal Properties Function Inverting analog input to the ACMP ...
Page 134
... Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 134 ACO ACF ACIE Description ACOPE ACMOD Freescale Semiconductor ...
Page 135
... ACF can be set on a rising edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge (toggle). The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPxO pin using ACOPE. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Analog Comparator (S08ACMPV2) 135 ...
Page 136
... Analog Comparator (S08ACMPV2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 136 Freescale Semiconductor ...
Page 137
... Section 10.1.4, “Temperature 2 Requires BGBE =1 in SPMSC1 see For value of bandgap voltage reference see MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor NOTE Table 10-1. ADC Channel Assignment Input Sensor”. Section 5.7.7, “System Power Management Status and Control 2 Register Section A.6, “ ...
Page 138
... ALTCLK input as ADCK ) ÷ m) Temp = 25 - ((V -V TEMP TEMP25 and m values from the ADC Electricals table. TEMP25 the cold slope value is applied in TEMP25 Equation 10-1. Equation 10-1 Eqn. 10-1 , and compares to TEMP Equation 10- TEMP Freescale Semiconductor ...
Page 139
... SSA V REFL = Not bonded to pins in 20-pin package = In 20-pin packages DDA REFH Figure 10-1. MC9S08EL32 Block Diagram Highlighting ADC Block and Pins MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor ANALOG COMPARATOR + (ACMP1) – OUT TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) ...
Page 140
... Chapter 10 Analog-to-Digital Converter (S08ADCV1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 140 Freescale Semiconductor ...
Page 141
... Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 10.1.6 Block Diagram Figure 10-2 provides a block diagram of the ADC module MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 141 ...
Page 142
... Figure 10-2. ADC Block Diagram Table 10-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...
Page 143
... This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...
Page 144
... Description Figure 10-4. Figure 10-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 10111 AD23 Freescale Semiconductor ...
Page 145
... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Input Select AD8 AD9 AD10 AD11 ...
Page 146
... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 146 Description ADR9 ADR8 Freescale Semiconductor ...
Page 147
... Figure 10-9. Compare Value Low Register(ADCCVL) 10.3.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor ADR5 ADR4 ADR3 ...
Page 148
... Description Table 10-6. Clock Divide Select Divide Ratio Table 10-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 10-7. ...
Page 149
... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 10-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...
Page 150
... ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 150 Description ADPC13 ADPC12 ADPC11 Description ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 151
... AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Description ADPC21 ADPC20 ...
Page 152
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 152 Description Freescale Semiconductor ...
Page 153
... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 153 ...
Page 154
... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 154 ). After f ADCK Freescale Semiconductor ...
Page 155
... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor frequency, precise sample time for continuous conversions ADCK ADICLK ADLSMP 0x, 10 ...
Page 156
... ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 156 NOTE Freescale Semiconductor ...
Page 157
... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor NOTE Conversions) is cleared when entering stop3 Table ...
Page 158
... Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Freescale Semiconductor ...
Page 159
... When available on a separate pin, both V as their corresponding MCU digital supply (V noise immunity and bypass capacitors placed as near as possible to the package. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ...
Page 160
... The input is sampled for on some devices. The low DDAD on some devices may be DDAD spec and the V potential (V DDAD must be connected to the same REFL . Setting the pin control register bits for and the input is equal to or REFL , the converter circuit converts it REFL Freescale Semiconductor REFH ...
Page 161
... I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 μF capacitor (C • improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor lower than REFH REFL ...
Page 162
... Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 162 LSB REFH REFL ). Note, if the last conversion is $3FE, then the LSB , one-time error. LSB Eqn. 10-2 . LSB ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...
Page 163
... Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) and will increase with noise. This error may be ...
Page 164
... Analog-to-Digital Converter (S08ADC10V1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 164 Freescale Semiconductor ...
Page 165
... SOPT1[IICPS] 0 (default Figure 11-1 shows the MC9S08EL32 Series and MC9S08SL16 Series block diagram with the IIC module highlighted. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor NOTE DD Table 11-1. IIC Position Options Port Pin for SDA PTA2 1 PTB6 ...
Page 166
... ANALOG-TO-DIGITAL 16 CONVERTER (ADC) is internally connected to V and internally connected SSA REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 . SS Freescale Semiconductor ...
Page 167
... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) 167 ...
Page 168
... This section consists of the IIC register descriptions in address order. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 168 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 169
... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor memory chapter of this document for the absolute address AD5 AD4 AD3 Figure 11-3. IIC Address Register (IICA) Table 11-2 ...
Page 170
... SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...
Page 171
... Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 11-5. IIC Divider and Hold Values SDA Hold ICR (Stop) (hex) Value 118 ...
Page 172
... IAAS W Reset Unimplemented or Reserved MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 172 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-6. IICC1 Field Descriptions Description BUSY 0 ARBL Figure 11-6. IIC Status Register (IICS RSTA SRW RXAK IICIF Freescale Semiconductor ...
Page 173
... Acknowledge received 1 No acknowledge received 11.3.5 IIC Data I/O Register (IICD Reset 0 0 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Table 11-7. IICS Field Descriptions Description DATA Figure 11-7. IIC Data I/O Register (IICD) Inter-Integrated Circuit (S08IICV2) 2 ...
Page 174
... This field is only valid when the ADEXT bit is set. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 174 Table 11-8. IICD Field Descriptions Description NOTE Figure 11-8. IIC Control Register (IICC2) Table 11-9. IICC2 Field Descriptions Description AD10 AD9 AD8 Freescale Semiconductor ...
Page 175
... SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Figure lsb msb ...
Page 176
... The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 176 11-9. There is one clock pulse on SCL for each data bit, the msb being Figure 11-9). Freescale Semiconductor ...
Page 177
... The first device to complete its high period pulls the SCL line low again. SCL1 SCL2 SCL Internal Counter Reset MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Delay Figure 11-10. IIC Clock Synchronization Inter-Integrated Circuit (S08IICV2) Figure 11-10). When all Start Counting High Period ...
Page 178
... The slave-transmitter remains addressed until it receives a stop condition ( repeated start condition (Sr) followed by a different slave address. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 178 Table 11-10). When a 10-bit address follows a start condition, R/W Slave Address 2nd byte AD[8:1] Table Data A ... Data A/A P 11-11 and including Freescale Semiconductor ...
Page 179
... Arbitration Lost 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Slave Address Slave Address 2nd byte 1st 7 bits A2 ...
Page 180
... A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 180 Freescale Semiconductor ...
Page 181
... IICS Module status flags IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT Address configuration MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Module Initialization (Slave) Module Initialization (Master) Register Model AD[7:1] ICR IICIE ...
Page 182
... Clear ARBL Y N IAAS=1 IAAS Data Transfer Address Transfer See Note 2 See Note 1 Y SRW=1 TX/ (Write) N ACK from Y Receiver ? N Read Data Tx Next from IICD Byte and Store Switch to Set RX Rx Mode Mode Dummy Read Dummy Read from IICD from IICD Freescale Semiconductor RX ...
Page 183
... The slave LIN interface controller (SLIC) is designed to provide slave node connectivity on a local interconnect network (LIN) sub-bus. LIN is an open-standard serial protocol developed for the automotive industry to connect sensors, motors, and actuators. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 185 ...
Page 184
... ANALOG-TO-DIGITAL 16 CONVERTER (ADC) is internally connected to V and internally connected SSA REFL PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 . SS Freescale Semiconductor ...
Page 185
... Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message framing constraints • Enhanced checksum (includes ID) generation and verification 1. Maximum bit rate of SLIC module dependent upon frequency of SLIC input clock. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 1 187 ...
Page 186
... MCU reset source is asserted. To prevent the SLIC DD(MIN) V > V (MIN) AND ANY DD DD MCU RESET SOURCE ASSERTED NO MCU RESET SOURCE ASSERTED INITREQ = 0; (INITACK = 0) SLCE SET IN SLCC2 REGISTER NETWORK ACTIVITY OR OTHER MCU WAKEUP SLIC WAIT drops below its DD rises above DD Freescale Semiconductor ...
Page 187
... This power conserving mode is automatically entered from the run mode whenever the CPU executes a STOP instruction the CPU executes a WAIT instruction and SLCWCM in SLCC1 is previously set. In this mode, the SLIC internal clocks are stopped. If SLIC interrupts are enabled (SLCIE = 1) prior to MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor is supplied to the internal DD 189 ...
Page 188
... Some aspects of SLIC module operation can be modified in special test mode. This mode is reserved for internal use only. 12.1.2.10 Low-Power Options The SLIC module can save power in disabled, wait, and stop modes. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 190 NOTE Freescale Semiconductor ...
Page 189
... SLIC Control Register 1 (SLCC1) SLIC control register 1 (SLCC1) contains bits used to control various basic features of the SLIC module, including features used for initialization and at runtime. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor SLCSV AND SLCF REGISTER CONTROL LIN PROTOCOL STATE MACHINE ...
Page 190
... This bit will be automatically cleared when the wakeup WAKETX symbol is complete. 0 Normal operation 1 Send wakeup symbol on LIN bus MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 192 INITREQ BEDD WAKETX Table 12-1. SLCC1 Field Descriptions Description NOTE TXABRT IMSG SLCIE Delay,” for details. Freescale Semiconductor ...
Page 191
... SLIC Control Register 2 (SLCC2) SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module Reset Unimplemented or Reserved Figure 12-5. SLIC Control Register 2 (SLCC2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Description RXFP SLCWCM BTM ...
Page 192
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 194 Table 12-2. SLCC2 Field Descriptions Description Section 12.6.18, “Digital Receive Section 12.6.6, “SLIC Module Initialization Table 12-3. Section 12.6.16, “Byte Transfer Mode Filter.” Procedure,” for more information on Operation,” for more detailed information Freescale Semiconductor ...
Page 193
... This setting is similar to choosing an input capture or output compare value for a timer. A write to both registers is required to update the bit time value. The SLIC bit time will not be updated until a write of the SLCBTL has occurred. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Max Filter Delay (in μs) Filter Input Clock (SLIC clock in MHz ...
Page 194
... Table 12-4. SLCBTH Field Descriptions Description SLIC.” Section 12.6.16, “Byte Transfer Mode BT5 BT4 BT3 Table 12-5. SLCBTL Field Descriptions Description SLIC.” Section 12.6.16, “Byte Transfer Mode BT10 BT9 BT8 Operation.” BT2 BT1 BT0 Operation.” Freescale Semiconductor ...
Page 195
... LIN module’s current state, which can be used with a user supplied jump table to rapidly enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state machine in software. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 5 4 INITACK ...
Page 196
... TX Message Buffer Empty Checksum Transmitted Message Buffer Empty Message Buffer Full Checksum Data Buffer Full No Errors Bit-Error Receiver Buffer Overrun Reserved Checksum Error Byte Framing Error Identifier Received Successfully Identifier Parity Error Reserved Reserved Wakeup Priority 0 (Lowest (Highest) Freescale Semiconductor ...
Page 197
... The checksum error occurs when the calculated checksum value does not match the expected value. If this error is encountered important to verify that the correct checksum calculation MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 23 SLIC clock counts since the reception of the last valid message. For ...
Page 198
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 200 NOTE Section 12.6.7, “Handling LIN Message Table 12-9 shows those interrupt sources which are Interrupt Source Interrupts Pending Message Buffer Empty Data Buffer Full No Errors Bit-Error Receiver Buffer Overrun Headers,” Priority 0 (Lowest Freescale Semiconductor ...
Page 199
... BTH:L does not match the bit rate of the incoming data. • • Wakeup The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC wait mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor Interrupt Source ...
Page 200
... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 202 5 4 DLC5 DLC4 DLC3 0 0 Table 12-10. SLCDLC Field Descriptions Description Table 12-11. Data Length Control Message Data Length (Number of Bytes) 0x00 1 0x01 2 0x02 3 ... ... 0x3D 62 0x3E 63 0x3F DLC2 DLC1 Freescale Semiconductor 0 DLC0 0 ...