DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 121
![BOARD DEMO FOR 9S08 EL MCU](/photos/9/23/92304/demo9s08el32_sml.jpg)
DEMO9S08EL32
Manufacturer Part Number
DEMO9S08EL32
Description
BOARD DEMO FOR 9S08 EL MCU
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08EL32.pdf
(356 pages)
2.DEMO9S08EL32.pdf
(14 pages)
3.DEMO9S08EL32.pdf
(2 pages)
Specifications of DEMO9S08EL32
Contents
Evaluation Board
Processor To Be Evaluated
MC9S08EL32
Data Bus Width
8 bit
Interface Type
RS-232, USB
Operating Supply Voltage
12 V
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08EL
Rohs Compliant
Yes
For Use With/related Products
MC9S08EL32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.3.2
Freescale Semiconductor
EREFSTEN
ERCLKEN
RANGE
EREFS
Field
BDIV
HGO
7:6
LP
5
4
3
2
1
0
Reset:
W
R
ICS Control Register 2 (ICSC2)
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00
01
10
11
Frequency Range Select — Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
External Reference Select — The EREFS bit selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
1 ICSERCLK active
0 ICSERCLK inactive
External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode
0 External reference clock is disabled in stop
before entering stop
Encoding 0 — Divides selected clock by 1
Encoding 1 — Divides selected clock by 2 (reset default)
Encoding 2 — Divides selected clock by 4
Encoding 3 — Divides selected clock by 8
0
7
BDIV
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Table 8-3. ICS Control Register 2 Field Descriptions
1
6
Figure 8-4. ICS Control Register 2 (ICSC2)
RANGE
0
5
HGO
0
4
Description
LP
0
3
EREFS
0
2
Internal Clock Source (S08ICSV2)
ERCLKEN EREFSTEN
1
0
0
0
121
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