DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 221

• Manufacturer Part Number: DEMO9S08EL32
• Description: BOARD DEMO FOR 9S08 EL MCU
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08EL32

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08EL32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 12 V
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08EL
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08EL32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
12.6.15 Bit Error Detection and Physical Layer Delay
The bit error detection circuitry of the SLIC module monitors the received bits to determine if they match
the state of the corresponding transmitted bits. The sampling of the receive line takes place near the end
of the bit being transmitted, so as long as the total physical layer delay does not exceed 75% of one bit
time, bit error detection will work properly. For normal LIN bus speeds (<= 20 kbps), the physical layer
delay in the system is typically significantly lower than 75% of a bit time and bit error detection should
remain enabled by the user.
If the physical layer delay begins to exceed 75% of one bit time, the received bits begin to significantly
lag behind the transmitted bits. In this case, it's possible for the bit error detection circuitry to falsely
sample the delayed 'previous' bit on the receive pin rather than the current bit. It is the responsibility of the
user to determine if the total physical layer delay is large enough to require disabling the bit error detection
circuitry. This should only be required at speeds higher than allowed in normal LIN operations.
Freescale Semiconductor
Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the
TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing
error.
(MHz)
clock
SLIC
20
18
16
14
12
10
2
8
6
4
2
Max Bit
(kbps)
312,500
281,250
250,000
218,750
187,500
156,250
125,000
Rate
15,625
93,750
62,500
31,250
Table 12-14. Digital Receive Filter Absolute Cutoff (Ideal Conditions)
RXFP = ÷8
RXFP = ÷4
Min Pulse
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Allowed
Width
(μs)
16.00
32.00
64.00
10.67
3.20
3.56
4.00
4.57
5.33
6.40
8.00
Max Bit
(kbps)
416,667
375,000
333,333
291,667
250,000
208,333
166,667
125,000
Rate
17,857
83,333
41,667
RXFP = ÷7
RXFP = ÷3
Min Pulse
Allowed
Width
(μs)
56.00
12.00
24.00
2.40
2.67
3.00
3.43
4.00
4.80
6.00
8.00
Max Bit
(kbps)
625,000
562,500
500,000
437,500
375,000
312,500
250,000
187,500
125,000
Rate
20,833
62,500
RXFP = ÷6
RXFP = ÷2
Min Pulse
Allowed
Width
(μs)
48.00
16.00
1.60
1.78
2.00
2.29
2.67
3.20
4.00
5.33
8.00
1,250,000
1,125,000
1,000,000
Max Bit
(kbps)
875,000
750,000
625,000
500,000
375,000
250,000
125,000
Rate
25,000
1
RXFP = ÷5
RXFP = ÷1
Min Pulse
Allowed
Width
(μs)
40.00
0.80
0.89
1.00
1.14
1.33
1.60
2.00
2.67
4.00
8.00
223