DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 125

• Manufacturer Part Number: DEMO9S08EL32
• Description: BOARD DEMO FOR 9S08 EL MCU
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08EL32

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08EL32
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 12 V
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08EL
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08EL32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.5
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 1024
times the reference frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for
BDC communications, and the external reference clock is enabled.
8.4.1.6
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external
reference clock is enabled.
8.4.1.7
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
ICSERCLK will be active in stop mode when all the following conditions occur:
8.4.2
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will
begin locking again after a few full cycles of the resulting divided reference frequency. The completion of
the switch is shown by the IREFST bit.
Freescale Semiconductor
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CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is active or LP bit is written to 0.
CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is not active and LP bit is written to 1.
IRCLKEN bit is written to 1
IREFSTEN bit is written to 1
ERCLKEN bit is written to 1
EREFSTEN bit is written to 1
Mode Switching
FLL Bypassed External (FBE)
FLL Bypassed External Low Power (FBELP)
Stop
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Internal Clock Source (S08ICSV2)
125