DEMO9S08EL32 Freescale Semiconductor, DEMO9S08EL32 Datasheet - Page 3

BOARD DEMO FOR 9S08 EL MCU

DEMO9S08EL32

Manufacturer Part Number
DEMO9S08EL32
Description
BOARD DEMO FOR 9S08 EL MCU
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets

Specifications of DEMO9S08EL32

Contents
Evaluation Board
Processor To Be Evaluated
MC9S08EL32
Data Bus Width
8 bit
Interface Type
RS-232, USB
Operating Supply Voltage
12 V
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08EL
Rohs Compliant
Yes
For Use With/related Products
MC9S08EL32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MC9S08EL32 Features
8-Bit HCS08 Central Processor Unit (CPU)
On-Chip Memory
Power-Saving Modes
Clock Source Options
System Protection
Development Support
• 40-MHz HCS08 CPU (central processor unit)
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
• FLASH read/program/erase over full operating
• EEPROM in-circuit programmable memory;
• Random-access memory (RAM)
• Security circuitry to prevent unauthorized access
• Two very low-power stop modes
• Reduced power wait mode
• Very low-power real-time interrupt for use in run,
• Oscillator (XOSC) — Loop-control Pierce
• Internal clock source (ICS) — Contains a
• Watchdog computer operating properly (COP)
• Low-voltage detection with reset or interrupt;
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH and EEPROM block protect
• Single-wire background debug interface
• Breakpoint capability allows single breakpoint
• In-circuit emulation (ICE) debug module —
voltage and temperature
program and erase while executing FLASH; erase
abort
to RAM and NVM contents
wait, and stop
oscillator; Crystal or ceramic resonator range of
31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
frequency-locked loop (FLL) controlled by internal
or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports
bus frequencies from 2–20 MHz
reset with option to run from dedicated 1-kHz
internal clock source or bus clock
selectable trip points
setting during in-circuit debugging (plus two more
breakpoints in the on-chip debug module)
contains two comparators and nine trigger modes;
eight-deep FIFO for storing change-of-flow
address and event-only data; supports both tag
and force breakpoints
Peripherals
Input/Output
Package Options
• ADC — 16-channel, 10-bit resolution, 2.5 μs
• ACMPx — Two analog comparators with
• SCI — Full duplex non-return to zero (NRZ); LIN
• SLIC — Supports LIN 2.0 and SAE J2602
• SPI — Full-duplex or single-wire bidirectional;
• IIC — Up to 100 kbps with maximum bus loading;
• TPMx — One 4-channel (TPM1) and one
• RTC — 8-bit modulus real-time counter with
• 22 general purpose I/O pins
• 16 interrupt pins with selectable polarity
• Hysteresis and configurable pull up device on all
• 28-TSSOP
• 20-TSSOP
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel; runs in stop3
selectable interrupt on rising, falling, or either
edge of comparator output; compare option to
fixed internal bandgap reference voltage; output
can optionally be routed to TPM module; runs in
stop3
master extended break generation; LIN slave
extended break detection; wake-up on active
edge
protocols; up to 120 kbps, full LIN message
buffering, automatic bit rate and frame
synchronization, checksum generation and
verification, UART-like byte transfer mode
double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data
transfer
2-channel (TPM2); selectable input capture,
output compare, or buffered edge- or
center-aligned PWM on each channel
binary or decimal based prescaler; external clock
source for precise time base, time-of-day,
calendar, or task scheduling functions; free
running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components
input pins; Configurable slew rate and drive
strength on all output pins.

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