MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1452

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Figure 21-60
21.7.1.1
This DWord specifies static information about the endpoint, in other words, this information does not
change over the lifetime of the endpoint. Device Controller software should not attempt to modify this
information while the corresponding endpoint is enabled.
21-118
1
2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
31–30
28–27
0
Mult zlt
Bits
Device controller read/write; all others read-only.
Offsets 0x08 through 0x20 contain the transfer overlay.
29
Name
Mult
00
zlt
—
Endpoint Capabilities/Characteristics
shows the Endpoint Queue Head structure.
Total Bytes
Mult. This field is used to indicate the number of packets executed per transaction description as given by
the following:
00 - Execute N Transactions as demonstrated by the USB variable length packet protocol where N is
computed using the Maximum Packet Length (dQH) and the Total Bytes field (dTD)
01 Execute 1 Transaction.
10 Execute 2 Transactions.
11 Execute 3 Transactions.
Note: Non-ISO endpoints must set Mult = 00.
Note: ISO endpoints must set Mult = 01, 10, or 11 as needed.
Zero length termination select. This bit is used to indicate when a zero length packet is used to terminate
transfers where to total transfer length is a multiple. This bit is not relevant for Isochronous transfers.
0 Enable zero length packet to terminate transfers equal to a multiple of the Maximum Packet Length.
1 Disable the zero length packet on transfers that are equal in length to a multiple Maximum Packet
Reserved, should be cleared. These bit reserved for future use and should be cleared.
Maximum Packet Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(default).
Length.
1
Table 21-74. Endpoint Capabilities/Characteristics
Figure 21-60. Endpoint Queue Head Layout
Current dTD Pointer
Next dTD Pointer
1
1
1
1
1
Set-up Buffer Bytes 3–0
Set-up Buffer Bytes 7–4
ioc
ios
15
Reserved
1
1
14
1
000
13 12 11
Description
MultO
1
1
10
1
000_0000_0000_0000
9
00
8
Current Offset
7
Reserved
Reserved
Reserved
Reserved
6
5
4
Status
1
Freescale Semiconductor
3
0000
0_0000
1
2
1
T
0
1
0x0C
0x1C
0x08
0x10
0x14
0x18
0x20
0x2C
0x00
0x04
0x24
0x28
offset
2
2
2
2
2
2
2