MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 658

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Enhanced Local Bus Controller

Offset OR0: 0x0_5004

OR1: 0x0_500c

OR2: 0x0_5014

OR3: 0x0_501c

OR4: 0x0_5024

OR5: 0x0_502c

OR6: 0x0_5034

OR7: 0x0_503c

EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read

shows the bit fields for ORn when the corresponding BRn[MSEL] selects the FCM machine.

Option Registers (OR n )—FCM Mode

access from the current bank and the next access.

External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).

0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)

1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by

LCRR[EADC]).

for the OR0 reset value. All other option registers have all bits cleared.

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 13-7. OR n

Figure 13-4. Option Registers (OR n ) in FCM Mode

PGS CSCT CST

The memory controller generates normal timing. No additional

cycles are inserted.

1 idle clock cycle is inserted.

4 idle clock cycles are inserted.

8 idle clock cycles are inserted.

GPCM Field Descriptions (continued)

Freescale Semiconductor

Access: Read/Write