MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 895

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

signals (MII) to 10 signals. To accomplish this objective, the data paths are halved in width and clocked at

twice the MII clock frequency, while clocks, carrier sense and error signals have been partly combined.

For 100 Mbps operation, the reference clock operates at 50 MHz, whereas for 10 Mbps operation, the

clock remains at 50MHz, but only every 10th cycle is used.

of the reduced media-independent interface and the signals required to establish an eTSEC’s connection

with a PHY. The RMII is implemented as defined by the RMII Specification of the RMII Consortium, as

of March 20, 1998.

Freescale Semiconductor

The management signals (MDC and MDIO) are common to all of the Ethernet controllers module

connections in the system, assuming that each PHY has a different management address.

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Reference Clock (TSEC n _TX_CLK)

Receive Control (RX_DV, RX_ER)

Figure 14-133. eTSEC-RMII Connection

Transmit Data (TSEC n _TXD[1:0])

Receive Data (TSEC n _RXD[1:0])

Management Data Clock

Management Data I/O

Transmit Control (TX_EN)

Figure 14-133

Enhanced Three-Speed Ethernet Controllers

depicts the basic components