MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 294

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-11
8-20
12–15
8–11
Bits
0–3
4–7
PRETOACT Precharge-to-activate interval (t
ACTTOPRE Activate to precharge interval (t
ACTTORW Activate to read/write interval for SDRAM (t
CASLAT
Name
describes TIMING_CFG_1 fields.
until an activate or refresh command is allowed.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
until a precharge command is allowed. This field is concatenated with TIMING_CFG_3[EXT_ACTTOPRE]
to obtain a 5-bit value for the total activate to precharge time. Note that the decode of 0000–0011 is equal
to 16-19 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 0, but it is equal to 0-3 clocks when
TIMING_CFG_3[EXT_ACTTOPRE] = 1.
0000 16 clocks
0001 17 clocks
0010 18 clocks
0011 19 clocks
0100 4 clocks
command until a read or write command is allowed.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
MCAS latency from READ command. Number of clock cycles between registration of a READ command
by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge
n
concatenated with TIMING_CFG_3[EXT_CASLAT] to obtain a 5-bit value for the total CAS latency. This
value must be programmed at initialization as described in
Configuration 2
0000 Reserved
0001 1 clock
0010 1.5 clocks
0011 2 clocks
0100 2.5 clocks
0101 3 clocks
0110 3.5 clocks
0111 4 clocks
and the latency is
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-11. TIMING_CFG_1 Field Descriptions
(DDR_SDRAM_CFG_2).”)
m
clocks, data is available nominally coincident with clock edge
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
RAS
0101 5 clocks
0110 6 clocks
0111 7 clocks
…
1111 15 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
1000 4.5 clocks
1001 5 clocks
1010 5.5 clocks
1011 6 clocks
1100 6.5 clocks
1101 7 clocks
1110 7.5 clocks
1111 8 clocks
RP
). Determines the number of clock cycles from a precharge command
). Determines the number of clock cycles from an activate command
RCD
Description
). Controls the number of clock cycles from an activate
Section 8.4.1.9, “DDR SDRAM Control
Freescale Semiconductor
n
+
m
. This field is