MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 675

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

describes LBCR fields.

Local bus disable

0 Local bus is enabled.

1 Local bus is disabled. No internal transactions will be acknowledged.

Defines the use of LBCTL

00 LBCTL is used as W/R control for GPCM or UPM accesses (buffer control).

01 LBCTL is used as LOE for GPCM accesses only.

10 LBCTL is used as LWE for GPCM accesses only.

11 Reserved.

Address hold disable. Removes part of the hold time for LAD with respect to LALE in order to lengthen the

0 During address phases on the local bus, the LALE signal negates one platform clock period prior to the

1 During address phases on the local bus, the LALE signal negates 0.5 platform clock period prior to the

Enables parity byte select on LGTA/LFRB/LGPL4/LUPWAIT/LPBSE signal.

0 Parity byte select is disabled. LGTA/LGPL4/LPBSE signal is available for memory control as LGPL4

1 Parity byte select is enabled. LPBSE signal is dedicated as the parity byte select output, and

Determines odd or even parity. Writing GPCM or UPM controlled memory with EPAR = 1 and reading the

memory with EPAR = 0 generates parity errors for testing.

0 Odd parity; normal, odd-parity ECC

1 Even parity; inverted, even-parity ECC

Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the

maximum count of bus clock cycles. For non-zero values of BMT, the number of LCLK clock cycles to count

down before a time-out error is generated is given by:

bus cycles = BMT × PS, where PS is set according to LBCR[BMTPS].

The value of BMT × PS must not be less than 40 bus cycles for reliable operation.

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

address being invalidated. For instance, at 33.3 MHz, this provides 3 ns of additional address hold time

at the external address latch.

address being invalidated. This halves the address hold time, but extends the latch enable duration. This

may be necessary for very high frequency designs.

(output) or LGTA/LFRB/LUPWAIT (input).

LGTA/LFRB/LUPWAIT is disabled.

Table 13-22. LBCR Field Descriptions

Enhanced Local Bus Controller