MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 243

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

Offset 0x2_0E4C

— DWNUM — TRANSSIZ BURST — TRANSSRC

describes L2ERRINTEN fields.

describes L2ERRATTR fields.

shows the L2 error attributes capture register (L2ERRATTR).

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 6-22. L2 Error Attributes Capture Register (L2ERRATTR)

Double-word number of the detected error (data ECC errors only)

Transaction size for detected error

Tag parity error reporting enable

0 Tag parity error reporting disabled

1 Tag parity error reporting enabled

Multiple-bit ECC error reporting enable. Note that uncorrectable read errors may cause the

assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it

is disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs,

L2ERRDIS[MBECCDIS] must be cleared and MBECCINTEN must be set to ensure that an

interrupt is generated. For more information, see the reference manual for the e500 core.

0 Multiple-bit ECC error reporting disabled

1 Multiple-bit ECC error reporting enabled

Single-bit ECC error reporting enable

0 Single-bit ECC error reporting disabled

1 Single-bit ECC error reporting enabled

L2 configuration error reporting enable

0 L2 configuration error reporting disabled

1 L2 configuration error reporting enabled

Table 6-18. L2ERRINTEN Field Descriptions

Table 6-19. L2ERRATTR Field Descriptions

L2 Look-Aside Cache/SRAM

Access: Read/Write