MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 535

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
58–60
62–63
0–48
Bits
49
50
51
52
53
54
55
56
57
61
Name
ERE
DSE
KSE
ICE
IFO
ME
PE
CE
AE
—
IE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-45. CRCU Interrupt Mask Register Bit Definitions
Reserved
Integrity Check Error. The supplied ICV(CRC) did not match the one computed by the
CRCU.
0 Integrity check error enabled. WARNING: Do not enable this if using EU status
1 Integrity check error disabled
Polynomial Error.
0 Polynomial error enabled
1 Polynomial error disabled
Internal Error. An internal processing error was detected while performing hashing.
0 Internal error enabled
1 Internal error disabled
Early Read Error. The CRCU register was read while the CRCU was performing
hashing.
0 Early read error enabled
1 Early read error disabled
Context Error. The CRCU key register, the key size register, the data size register, or
the mode register, was modified while the CRCU was performing hashing.
0 Context error enabled
1 Context error disabled
Key Size Error. A value outside the bounds was written to the CRCU key size register
0 Key size error enabled
1 Key size error disabled
Data Size Error. An inconsistent value was written to the CRCU data size register:
0 Data size error enabled
1 Data size error disabled
Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address Error. An illegal read or write address was detected within the CRCU address
space.
0 Address error enabled
1 Address error disabled
Reserved
Input FIFO Overflow. The CRCU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Reserved
writeback (see bits IWSE and AWSE in
Register
(CCR)”).
Description
Section 10.4.4.1, “Channel Configuration
Security Engine (SEC) 3.0
10-105