MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 413

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.7.3
The IIVPRs, shown in
to the internal interrupt sources listed in
Section 9.4.1, “Flow of Interrupt Control,”
Freescale Semiconductor
Offset IIVPR0–7 0x0200, 0x0220, 0x0240, 0x0260, 0x0280, 0x02A0, 0x02C0, 0x02E0
3–29
Reset
Bits Name
30
31
2
W
R
IIVPR8–15 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03A0, 0x03C0, 0x03E0
IIVPR16–23 0x0400, 0x0420, 0x0440, 0x0460, 0x0480, 0x04A0, 0x04C0, 0x04E0
IIVPR24–31 0x0500, 0x0520, 0x0540, 0x0560, 0x0580, 0x05A0, 0x05C0, 0x05E0
IIVPR32–39 0x0600, 0x0620, 0x0640, 0x0660, 0x0680, 0x06A0, 0x06C0, 0x06E0
IIVPR40–47 0x0700, 0x0720, 0x0740, 0x0760, 0x0780, 0x07A0, 0x07C0, 0x07E0
IIVPR48–55 0x0800, 0x0820, 0x0840, 0x0860, 0x0880, 0x08A0, 0x08C0, 0x08E0, IIVPR56–63
0x0900, 0x0920, 0x0940, 0x0960, 0x0980, 0x09A0, 0x09C0, 0x09E0
MSK
CI1
P1
P0
—
1
0
Critical interrupt 1. Ci n fields should be set only for level-sensitive external interrupts (EIVPR n [S]= 1). Setting them
for edge-sensitive does not provide reliable interrupt response. Reserved in single-processor implementations.
0 Processor core 1 does not receive this interrupt.
1 Directs the external interrupt to processor core 1 by causing the cint1 output signal from the PIC to assert. See
Reserved, should be cleared.
Processor core 1. Indicates whether processor core 1 receives the interrupt through int.
0 Processor core 1 does not receive this interrupt.
1 Directs the interrupt to processor core 1 through the assertion of int1 .
Note: Reserved in single-processor implementations.
Processor core 0. Indicates whether processor core 0 receives the interrupt.
0 Processor core 0 does not receive this interrupt.
1 Directs the interrupt to processor core 0 through the assertion of int0 .
The default destination is for processor core 0 to receive this external interrupt after the PIC is reset.
A
0
1
Internal Interrupt Vector/Priority Registers (IIVPR n )
Section 9.1.2, “Interrupts to the Processor Core.”
0
Because all internal interrupts are active-high, clearing the polarity field,
IIVPRn[P], disables that interrupt. Care should be taken to ensure this field
is set during initialization and that it is not inadvertently corrupted when
loading or reloading IIVPRs with priority, mask, or vector data.
2
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Figure 9-40. Internal Interrupt Vector/Priority Registers (IIVPRs)
Figure
—
0
0
Table 9-39. EIDR n Field Descriptions (continued)
9-40, have the same fields and format as the GTVPRs, except that they apply
7
0
P
8
0
0
9
—
Table
0
for information on IPR and ISR.
11 12
0
9-3. These interrupts are all level-sensitive. See
0
PRIORITY
NOTE
0
Description
0
15 16
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0
Programmable Interrupt Controller (PIC)
VECTOR
Access:
Mixed
9-43
31
0