MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 374

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.1.2
The external interrupt signal, int, is the main interrupt output from the PIC to the processor core.
The interrupt sources can also specify the critical interrupt output, cint, if the corresponding xIDRn[CI0]
or xIDRn[CI1] is set.
The PIC also defines the PIR, described in
which can be used to reset the core. Processor core interrupts generated by the PIC are described in
Table
9.1.3
Mixed or pass-through mode of operation is chosen by setting or clearing GCR[M], as described in
Section 9.3.1.4, “Global Configuration Register (GCR).”
9-4
•
•
External interrupt
Critical interrupt
Machine check
Unconditional
debug event
Reset
Core Interrupt
9-1.
Support for connection of external interrupt controller device such as an 8259 programmable
interrupt controller. In 8259 mode, an interrupt causes assertion of a local (that is, internal to the
integrated device) interrupt output signal.
Pass-through mode (PIC disabled) in which the PIC directs interrupts off-chip for external
servicing. See
Type
Interrupts to the Processor Core
Modes of Operation
Table 9-1. Processor Interrupts Generated Outside the Core—Types and Sources
(Input to Core)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
coren_hreset • HRESET assertion (and negation)
Signaled by
coren_mcp
coren_ude
Section 9.1.3.2, “Pass-Through Mode (GCR[M] =
cint
int
Other Interrupts Generated Outside the Core
Generated by the PIC, as described in
Generated by the PIC, as described in
• MCP
• SRESET
• Assertion of core_mcp by global utilities block
UDE. Asserting UDE generates an unconditional debug exception type debug
interrupt and sets a bit in the debug status register, DBSR[UDE], as described in
Section 6.13.2, “Debug Status Register (DBSR).”
• core_hreset_req . Output from core—caused by writing to the core DBCR0[RST].
• core_reset . Output from PIC. See
This condition is additionally qualified with MSR[DE] and DBCR0[IDM] bits.
Note that assertion of this signal causes a hard reset of the core only.
core_hreset_req can also be caused by a second timer timeout condition as
described in
Register (PIR).”
PIC-Programmable Interrupts
Section 9.3.1.6, “Processor Core Initialization Register
Section 9.3.2.6, “Timer Control Registers (TCRA–TCRB).”
Section 9.3.1.6, “Processor Core Initialization
Sources
Section 9.1.4, “Interrupt Sources.”
Section 9.1.4, “Interrupt Sources.”
0).”
Freescale Semiconductor
(PIR),”