MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 203

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

fields in the first 0x52 addressable bytes. Therefore, FAT32 filesystem compatibility is only possible if
used in a system in which this boot sector information is not required.
Also note that the user code is copied from one sequential area of SD/MMC card memory space specified
by the Source Address. The boot ROM software does not look for or parse any File Allocation Table, and
furthermore, the boot ROM software assumes that the User Code is in one contiguous range of memory
addresses.
4.5.1.1.4
The eSDHC controller configuration is used by the boot ROM software. After the boot from eSDHC has
finished, the user can change this configuration for other uses of the eSDHC interface. The boot ROM
software also changes some of this configuration automatically depending upon the features supported by
the SD/MMC card that is connected.
The eSDHC controller is initially configured to operate in the following configuration:
4.5.1.1.5
The code in the eSDHC Boot ROM configuration performs the following sequence of events:
Freescale Semiconductor
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1. The eSDHC controller is configured as per
2. Card-detect.
3. The SD/MMC card is reset.
4. SD/MMC card voltage validation is performed.
5. SD/MMC card identification.
6. With CMD9, the CSD (Card-Specific Data) register of the SD/MMC card is read.
Address Invariant Mode (eSDHC.PROTCTL[EMODE]=10)
SDHC_DAT[3] does not monitor card insertion. The GPIO4/SDHC_CD pin is used for card detect
(eSDHC.PROTCTL[D3CD]=0 and Global_Utilities.PMUXCR[SDHC_CD]=1).
1-bit mode (eSDHC.PROTCTL[DTW]=00)
SDCLK at 400 kHz or below, but higher than 100 kHz (for MPC8536E platform frequency up to
66 MHz, and therefore eSDHC base clock frequency up to 333 MHz). This is done with
eSDHC.SYSCTL[SCLKFS]=0x20 and eSDHC.SYSCTL[DVS]=0xC, for a divisor of 832.
There must be precisely one device connected on the eSDHC bus (and this device must be inserted
prior to boot). Multiple MMC devices sharing the one bus are not supported.
The bus operates in push-pull mode (MPC8536E pads drive both logic “0” and logic “1” as
appropriate). If a MMC card is to be connected, then weak external pull-ups are required on the
SDHC_CMD and SDHC_DAT[] pins in order to interface with the MMC open-drain mode during
initialisation.
The eSDHC DMA engine is not used for Control or Configuration Word accesses; instead, all
eSDHC data transfers are initiated by the processor core polling eSDHC.PRSSTAT[BRR] and
accessing data through the DATPORT register (XFERTYP[DMAEN]=0). The eSDHC DMA
engine is used for User Code accesses.
Configuration”.
eSDHC Controller Initial Configuration
eSDHC Controller Boot Sequence
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 4.5.1.1.4, “eSDHC Controller Initial
Reset, Clocking, and Initialization
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