MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 192

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.4.3.18
The PCI clock source inputs, shown in
for the PCI interface. See Section
information. Note that the value latched on this signal during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register
4.4.3.19
The PCI speed configuration input, shown in
with the PCI clock frequencies in use. The default setting is appropriate for PCI operating above 33 MHz;
for low speed operation (PCI at or below 33 MHZ) this POR configuration input should be low during
HRESET. If this configuration is not set properly, behavior of the PCI interface may be unreliable.
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDEVSR, described in
4.4.3.20
The PCI I/O impedance configuration inputs, shown in
drivers for the respective interfaces. Note that the values latched on these signals during POR are
accessible through PORIMPSCR, described in
Register (PORIMPSCR).”
4-22
Functional Signal
USB1_STP
Functional
Default (1)
Signal
PCI_GNT1
Default (1)
Functional Signal Reset Configuration Name
USB2_STP
Default (1)
Reset Configuration
PCI Clock Selection
PCI Speed Configuration
PCI I/O Impedance
(PORDEVSR).”
cfg_pci_clk
Name
Reset Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
cfg_pci_impd
Name
Section 23.4.1.4, “POR Device Status Register (PORDEVSR).”
cfg_pci_speed
(Binary)
Value
Section 4.4.4.1, “System Clock/PCI Clock/DDR
0
1
Table 4-27. PCI Speed Configuration
Table 4-28. PCI I/O Impedance
Table
Table 4-26. PCI Clock Select
Asynchronous mode. PCI_CLK is used as the clock for the PCI interface
Synchronous mode. SYSCLK is used as the clock for the PCI interface (default).
(Binary)
Value
4-26, specify the clock mode (synchronous or asynchronous)
0
1
Table
Section 23.4.1.3, “POR I/O Impedance Status and Control
(Binary)
25- I/O drivers are used on the PCI interface.
42-
Value
4-27, configures internal logic for proper operation
0
1
Table 4-28
I/O drivers are used on the PCI interface (default).
PCI frequency at or below 33 MHz
PCI frequency above 33 MHz (default)
select the impedance of the PCI I/O
Meaning
Section 23.4.1.4, “POR Device
Meaning
Meaning
Clock” for more
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