MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 802

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Offset eTSEC1:0x2_4300;

Enhanced Three-Speed Ethernet Controllers

The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must

be written only after a system reset (at initialization) or after a graceful receive stop has completed.

Figure 14-24

eTSEC3:0x2_6300

LFC VLEX FILREN FSQEN GHTX IPCSEN TUCSEN

describes the fields of the RCTRL register.

describes the RCTRL register.

Receive Control Register (RCTRL)

Layer 2 offset. The number of octet pairs from the start of the frame that the parser should expect to see

before the first byte of the Ethernet DA.

For frames received over Ethernet, the start of frame is regarded as the SFD symbol.

For packets received through the FIFO packet interface the start of frame is regarded as the first octet of

receive data.

The user may think of this value as representing the length - in multiples of two bytes - of a ‘shim’ header

that is inserted between the SFD and DA. By writing to RCTRL with a mask of 0xFE00_0000, the even

byte length restriction is guaranteed.

For normal frames, this field should be left as 0.

Time stamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less

than 8. Must be set to zero if TMR_CTRL[TE]=0.

Packet alignment padding length. If not zero, PAL (1–31) bytes of zero padding are inserted before the

start of each received frame, but following the RxFCB if TOE is enabled. For Ethernet where optional

preamble extraction is enabled, the padding appears before the preamble, otherwise the padding

precedes the layer 2 header. The value of PAL can be set so that the start of the IP header in the receive

data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure

such alignment of the IP header.

Note that the minimum zero padding value for this field should be PAL–8 if the TS field is set and 0 when

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 14-24. RCTRL Register Definition

Table 14-29. RCTRL Field Descriptions

PRSFM BC_REJ PROM RSF EMEN —

Freescale Semiconductor

Access: Read/Write