MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 236

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM

The L2 memory-mapped SRAM base address registers (L2SRBARn), shown in

lower 18 bits of the 22-bit SRAM base address.

L2SRBAR bits are described in

When enabled, the windows defined in L2SRBARn and L2SRBAREAn supersede all other mappings of

these addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must

never overlap configuration space as defined by CCSRBAR (see

Control, and Status Registers Base Address Register

windows is discouraged because processor and snoopable I/O transactions would map to the SRAM while

non-snooped I/O transactions would be mapped by the local access windows. Only if all accesses to the

SRAM address range are snoopable can results be consistent if SRAM and local access windows overlap.

Offset 0x2_0100

ADDR Contains the lower 18 bits of the 22-bit L2 memory-mapped SRAM base address; the upper 4 bits are

Figure 6-11. L2 Memory-Mapped SRAM Base Address Registers (L2SRBAR n )

contained in L2SRBAREA n [ADDR]. (Note that some of these bits may not be needed, depending on how the

L2 cache is partitioned.) The combined base address from L2SRBAREA n [ADDR] || L2SRBAR n [ADDR] is

used as follows:

SRAM Partition

Unused bits of the base address are masked off by the hardware.

L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBAR n )

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Bits Required for SRAM Offset

Table 6-8. L2SRBAR n Field Descriptions

(CCSRBAR).”) Overlapping SRAM and local access

Bits Used for Actual Base Address

Section 4.3.1.1.2, “Configuration,

Freescale Semiconductor

Access: Read/Write

6-11, contain the