MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 417

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The registers in

multi-core device. The OpenPIC interface specifies that a copy of these registers be available to each core

at the same physical address by using the ID of the processor core that initiates the transaction to determine

the set of per-CPU registers to access.

These addresses, shown in

in what is called the private access space. This duplication allows user code to execute correctly in an

multiprocessor environment without needing to know which core it is running on. On a single-core device,

each register has two addresses, one in the normal address space and one in the private access space. It is

included on even single-core devices to simplify the porting of such code.

accessing a register normally, each core sources a different address. However, when accessing the same

Freescale Semiconductor

shows how the duplicated registers are addressed in a four-core device Note that when

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 9-44. Per-CPU Registers—Private Access Address Offsets

Interprocessor 0 dispatch register (IPIDR0)

Interprocessor 1 dispatch register (IPIDR1)

Interprocessor 2 dispatch register (IPIDR2)

Interprocessor 3 dispatch register (IPIDR3)

Current task priority register (CTPR)

Who am I register (WHOAMI0)

Interrupt acknowledge register (IACK)

End of interrupt register (EOI)

are called per-CPU registers because they are duplicated for each core in a

9-44, appear in the memory map at the same offset for every processor

Programmable Interrupt Controller (PIC)