MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 518

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.1.12.1 AESU FIFOs
AESU uses an input FIFO/output FIFO pair to hold data before and after the encryption process. Normally,
the channels control all access to these FIFOs. For host-controlled operation, a write to anywhere in the
AESU FIFO address space enqueues data to the AESU input FIFO, and a read from anywhere in the AESU
FIFO address space dequeues data from the AESU output FIFO.
Writes to the input FIFO go first to a staging register which can be written by byte, word (4 bytes), or dword
(8 bytes). When all 8 bytes of the staging register have been written, the entire dword is automatically
enqueued into the FIFO. If any byte is written twice between enqueues, it causes an error interrupt of type
AE from the EU. When writing the last portion of data, it is not necessary to write all 8 bytes. Any last
bytes remaining in the staging register are automatically padded with zeros and forced into the input FIFO
when the AESU end of message register is written.
The output FIFO is readable by byte, word, or dword. When all 8 bytes of the head dword have been read,
that dword is automatically dequeued from the FIFO so that the next dword (if any) becomes available for
reading. If any byte is read twice between dequeues, it causes an error interrupt of type AE from the EU.
Overflows and underflows caused by reading or writing the AESU FIFOs are reflected in the AESU
interrupt status register.
The AESU fetches data 128 bits at a time from the input FIFO. During processing, the input data is
encrypted or decrypted and the results are placed in the output FIFO. The output size is the same as the
input size.
The input FIFO may be written any time the number of dwords currently in the input FIFO (as indicated
by the IFL field of the AESU status register) is less than 32. There is no limit on the total number of bytes
in a message. The number of bits in the final message block must be set in the data size register.
The output FIFO may be read any time the OFR signal is asserted (as indicated in the AESU status
register). This indicates that the number of bytes in the output FIFO is at or above the threshold specified
in the mode register.
10.7.2
ARC4 Execution Unit (AFEU)
This section contains details about the ARC4 execution unit (AFEU), including modes of operation, status
and control registers, S-box memory, and FIFOs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the AFEU is used through channel-controlled access,
which means that most reads and writes of AFEU registers are directed by the SEC channels. Driver
software would perform host-controlled register accesses only on a few registers for initial configuration
and error handling.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-88
Freescale Semiconductor