MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 1506

Manufacturer Part Number

BOARD REF COMEXPRESS MPC8536

Manufacturer

Freescale Semiconductor

PowerQUICC ™r

CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Global Utilities

GENCFGR is shown in

alternate functions on GPIO, on local bus chip select pins LCS[5:7], and interrupt input pins IRQ[9:11],

respectively. Specifically, DMA request, acknowledge, and done signals comprise the secondary functions

for the associated IRQ and local bus chip select signals.

It contains also the SPI/ eSDHC, GPIO/eSDHC, GPIO/USB1, GPIO/USB2 and GPIO/PCI controls for

0–31 POR_CFG_VEC General-purpose POR configuration vector sampled from local bus address/data signals at the

Offset 0x030

describes the bit settings of GENCFGR.

describes the bit settings of GPPORCR.

General Configuration Register (GENCFGR)

Alternate Function Signal Multiplex Control Register (PMUXCR)

23-9, PMUXCR contains bits that enable DMA channels 0, 1, 2 and 3 which exist as

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

negation of HRESET. Note that if nothing is driven on these signals during reset, the value of this

Figure 23-8. General Configuration Register (GENCFGR)

Secure digital WP polarity

0 SDHC_WP is active high (0=write enabled, 1=write protected).

1 SDHC_WP is active low (0=write protected, 1=write enabled).

Note: This bit should be set to 1 if PMUXCR[SDHC_WP]=0 (SDHC_WP not exposed to pins)

and eSDHC write functionality is required.

Table 23-10. GPPORCR Field Descriptions

Table 23-11. GENCFGR Field Descriptions

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