MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 798

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-22
14.5.3.2.8
The TBDBPH register is written by the user with the most significant address bits common to all TxBD
buffer addresses, TxBD[Data Buffer Pointer]. As a consequence, all Tx buffers must be placed in a 4
gigabyte segment of memory whose base address is prefixed by the bits in TBDBPH. The TxBD ring itself
can reside in a different memory region (based at TBASEH).
TBDBPH register.
Table 14-25
14.5.3.2.9
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring.
of their ring’s associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be
14-50
16–23
24–31
28–31
8–15
0–27
Bits
Bits
0–7
Offset
Reset
W
R
Name
TBDBPH Most significant bits common to all data buffer addresses contained in TxBDs. The user must initialize
WT5
WT6
WT7
WT4
0
Name
—
describes the fields of the TR47WT register.
describes the fields of the TBDBPH register.
Transmit Data Buffer Pointer High Register (TBDBPH)
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4
prevents transmission.
Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5
prevents transmission.
Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6
prevents transmission.
Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7
prevents transmission.
eTSEC1:0x2_4180;
Reserved
TBDBPH before enabling the eTSEC transmit function.
eTSEC3:0x2_6180
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-19
64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
Figure 14-18. TBDBPH Register Definition
Table 14-23. TBDBPH Field Descriptions
Table 14-22. TR47WT Field Descriptions
describes the TBPTR registers. These registers takes on the value
—
All zeros
Description
Description
Figure 14-18
describes the definition for the
Freescale Semiconductor
Access: Read/Write
27 28
TBDBPH
31