MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 923

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.3.12 Internal and External Loop Back
Setting MACCFG1[Loop Back] causes the MAC transmit outputs to be looped back to the MAC receive
inputs. Clearing this bit results in normal operation. This bit is cleared by default. Clearing this bit results
in normal operation.
14.6.3.13 Error-Handling Procedure
The eTSEC reports frame reception and transmission error conditions using the channel BDs, the error
counters, and the IEVENT register.
Transmission errors are described in
Reception errors are described in
Freescale Semiconductor
Overrun error
Busy error
Transmitter underrun
Retransmission
attempts limit expired
Late collision
Memory read error
Data parity error
Babbling transmit error
Error
Error
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer
overrun occurs, the controller sets RxBD[OV], sets RxBD[L], closes the buffer, increments the
discarded frame counter (RDRP), and sets IEVENT[RXF], The receiver then enters hunt mode
(seeking start of a new frame).
A frame is received and discarded due to a lack of buffers. The controller sets IEVENT[BSY] and
increments the discarded frame counter (RDRP). In addition, the RSTAT[QHLT n ] bit is set. RDRP
increments for each frame that is received while the receiver is halted due to a busy condition. The
halted queue resumes reception once the RSTAT[QHLT n ] bit is cleared.
Transmitter underrun can occur either after frame transmission has commenced, or in response to an
incomplete sequence of TxBDs. In the former case, the controller sends 32 bits that ensure a CRC
error, and terminates buffer transmission. In the latter case, the relevant transmit queue is halted. In
all cases, the eTSEC closes the buffer, sets TxBD[UN], IEVENT[XFUN], and IEVENT[TXE]. The
controller resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, IEVENT[CRL], and
IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
The controller terminates buffer transmission, sets TxBD[LC], closes the buffer, IEVENT[LC], and
IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT] is cleared (and
DMACTRL[GTS] is cleared).
A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR], DMA
stops sending data to the FIFO which causes an underrun error, and therefore TxBD[UN] is set, but
IEVENT[XFUN] is not set. The TSTAT[THLT] is set. Transmits are continued once TSTAT[THLT] is
cleared.
Data in the transmit FIFO was potentially corrupted. The controller sets IEVENT[DPE], but otherwise
continues transmission until halted explicitly.
A frame is transmitted which exceeds the MAC’s Maximum Frame Length and
MACCFG2[Huge Frame] is a 0. The controller sets IEVENT[BABT] and continues without interruption.
Table
Table 14-156. Transmission Errors
Table
Table 14-157. Reception Errors
14-157.
14-156.
Description
Response
Enhanced Three-Speed Ethernet Controllers
14-175