HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 134

SH 1 CORE 32B MPU, 20MHZ/5V, 100

HD6417020SX20IV

Manufacturer Part Number
HD6417020SX20IV
Description
SH 1 CORE 32B MPU, 20MHZ/5V, 100
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SX20IV

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Bit 12: PCHK1
0
1
• Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.11
RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write.
Data requires a password when it is written. This prevents data from being mistakenly overwritten
by program overruns and the like.
Writing to RCR, RTCSR, RTCNT, and RTCOR: Use only word transfer instructions. You
cannot write with byte transfer instructions. As figure 8.2 shows, when writing to RCR, place
H'5A in the upper byte and the write data in the lower byte. When writing to RTCSR, place H'A5
in the upper byte and the write data in the lower byte. When writing to RTCNT, place H'69 in the
upper byte and the write data in the lower byte. When writing to RTCOR, place H'96 in the upper
byte and the write data in the lower byte. These transfers write data in the lower byte to the
respective registers. If the upper byte differs from the above passwords, no writing occurs.
Reading from RCR, RTCSR, RTCNT, and RTCORP: These registers are read like other
registers. They can be read by byte and word transfer instructions. If read by word transfer, the
value of the upper eight bits is H'00.
114 RENESAS
Notes on Register Access
RTCOR
RTCSR
RTCNT
RCR
Figure 8.2 Writing to RCR, RTCSR, RTCNT, and RTCOR
Bit 11: PCHK0
0
1
0
1
15
15
15
15
H'5A
H'A5
H'69
H'96
Description
Parity not checked and not generated (initial value)
Parity checked and generated only in DRAM area
Parity checked and generated in DRAM area and area 2
Reserved
8 7
8 7
8 7
8 7
Write data
Write data
Write data
Write data
0
0
0
0

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